EVAL-SSM2518Z AD [Analog Devices], EVAL-SSM2518Z Datasheet - Page 26

• Manufacturer Part Number: EVAL-SSM2518Z
• Description: Digital Input Stereo, 2 W, Class-D
• Manufacturer: AD [Analog Devices]

REGISTER (REG_MAP) DETAILS
SOFTWARE RESET AND MASTER SOFTWARE POWER-DOWN CONTROL REGISTER
Address: 0x00, Reset: 0x05, Name: Reset_Power_Control
Table 13. Bit Descriptions for Reset_Power_Control
Bits
7
6
5
[4:1]
0
SSM2518
Bit Name
S_RST
RESERVED
NO_BCLK
MCS
SPWDN
Settings
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
0
1
0
1
0
1
Description
Software Reset. Write 1 to reset all internal blocks, including I
to their initial state.
Normal operation
Software reset
Reserved.
Bit Clock Source Selection. Either the MCLK or BCLK pin can be routed
internally to the bit clock.
BCLK pin used as bit clock source. Typical configuration.
MCLK pin used as bit clock source. No BCLK pin connection is needed.
Master Clock Select. This must match the ratio between the input MCLK
frequency and the audio sample rate, as shown in Table 11.
64 × f
128 × f
256 × f
384 × f
512 × f
768 × f
100 × f
200 × f
400 × f
Reserved
Software Master Power-Down. This places all blocks, except the I
interface, into a low power state.
Normal operation
Software master power-down
S
S
S
S
S
S
S
S
S
Rev. A | Page 26 of 48
2
C registers,
2
C
Data Sheet
Reset
0x0
0x0
0x0
0x2
0x1
Access
RW
RW
RW
RW
RW