HEF4007UBT,652 NXP Semiconductors, HEF4007UBT,652 Datasheet - Page 2

• Manufacturer Part Number: HEF4007UBT,652
• Description: IC DUAL PAIR/INVERTER 14SOIC
• Manufacturer: NXP Semiconductors
• Series: 4000Br

Specifications of HEF4007UBT,652

• Logic Type: Configurable Multiple Function
• Number Of Circuits: 2
• Number Of Inputs: 1
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Logic Family: HEF4000
• Number Of Channels Per Chip: 3
• Polarity: Inverting
• Supply Voltage (max): 15 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• High Level Output Current: - 3.6 mA
• Low Level Output Current: 3.6 mA
• Minimum Operating Temperature: - 40 C
• Number Of Lines (input / Output): 3 / 3
• Propagation Delay Time: 80 ns at 5 V, 40 ns at 10 V, 30 ns at 15 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Operating Temperature: -
• Output Type: -
• Current - Output High, Low: -
• Schmitt Trigger Input: -
• Lead Free Status / Rohs Status: Details
• Other names: 933372620652; HEF4007UBTD; HEF4007UBTD

Philips Semiconductors
DESCRIPTION
The HEF4007UB is a dual complementary pair and an inverter with access to each device. It has three n-channel and
three p-channel enhancement mode MOS transistors.
January 1995
HEF4007UBP(N):
HEF4007UBD(F):
HEF4007UBT(D):
( ): Package Designator North America
Dual complementary pair and inverter
Fig.2 Pinning diagram.
14-lead DIL; plastic
(SOT27-1)
14-lead DIL; ceramic (cerdip)
(SOT73)
14-lead SO; plastic
(SOT108-1)
Fig.1 Schematic diagram.
2
PINNING
FAMILY DATA, I
See Family Specifications for V
S
D
D
S
D
G
P2
P1
N1
N2
N/P3
1
to G
, S
, S
, D
, D
P3
N3
P2
N2
3
source connections to 2nd and 3rd
p-channel transistors
drain connections from the 1st and 2nd
p-channel transistors
drain connections from the 1st and 2nd
n-channel transistors
source connections to the 2nd and 3rd
n-channel transistors
common connection to the 3rd p-channel
and n-channel transistor drains
gate connections to n-channel and
p-channel of the three transistor pairs
DD
LIMITS category GATES
IH
/V
Product specification
IL
HEF4007UB
unbuffered stages
gates