74ACT573SCX Fairchild Semiconductor, 74ACT573SCX Datasheet

IC LATCH OCTAL HS 3STATE 20-SOIC

74ACT573SCX

Manufacturer Part Number
74ACT573SCX
Description
IC LATCH OCTAL HS 3STATE 20-SOIC
Manufacturer
Fairchild Semiconductor
Series
74ACTr
Datasheet

Specifications of 74ACT573SCX

Logic Type
D-Type Transparent Latch
Circuit
8:8
Output Type
Tri-State
Voltage - Supply
4.5 V ~ 5.5 V
Independent Circuits
1
Delay Time - Propagation
6ns
Current - Output High, Low
24mA, 24mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-SOIC (7.5mm Width)
Dc
0136
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74ACT573SCX
74ACT573SCXTR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74ACT573SCX
Manufacturer:
FAIRCHILD
Quantity:
1 105
© 1999 Fairchild Semiconductor Corporation
74AC573 • 74ACT573
Octal Latch with 3-STATE Outputs
General Description
The 74AC573 and 74ACT573 are high-speed octal latches
with buffered common Latch Enable (LE) and buffered
common Output Enable (OE) inputs.
The 74AC573 and 74ACT573 are functionally identical to
the 74AC373 and 74ACT373 but with inputs and outputs
on opposite sides.
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
FACT
Order Number
74AC573SC
74AC573SJ
74AC573MTC
74AC573PC
74ACT573SC
74ACT573SJ
74ACT573MTC
74ACT573PC
is a trademark of Fairchild Semiconductor Corporation.
Package Number
MTC20
MTC20
IEEE/IEC
M20D
M20D
M20B
M20B
N20A
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS--013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS--013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
DS009973
Features
Connection Diagram
Pin Descriptions
I
Inputs and outputs on opposite sides of package allow-
ing easy interface with microprocessors
Useful as input or output port for microprocessors
Functionally identical to 74AC373 and 74ACT373
3-STATE outputs for bus interfacing
Outputs source/sink 24 mA
74ACT573 has TTL-compatible inputs
CC
D
LE
OE
O
and I
Pin Names
0
0
Package Description
–D
–O
7
7
OZ
reduced by 50%
Data Inputs
Latch Enable Input
3-STATE Output Enable Input
3-STATE Latch Outputs
November 1988
Revised October 1999
Description
www.fairchildsemi.com

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74ACT573SCX Summary of contents

Page 1

... Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC FACT is a trademark of Fairchild Semiconductor Corporation. © 1999 Fairchild Semiconductor Corporation Features I and I ...

Page 2

Functional Description The 74AC573 and 74ACT573 contain eight D-type latches with 3-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the D inputs enters the latches this condition the latches are transparent, i.e., a ...

Page 3

Absolute Maximum Ratings Supply Voltage ( Input Diode Current ( 0. 0. Input Voltage ( Output Diode Current ( ...

Page 4

AC Electrical Characteristics for AC Symbol Parameter t Propagation Delay PHL PLH Propagation Delay PLH PHL n t Output Enable Time PZL t PZH t Output Disable Time PHZ ...

Page 5

DC Electrical Characteristics for ACT V Symbol Parameter V Minimum HIGH Level 4.5 IH Input Voltage 5.5 V Maximum LOW Level 4.5 IL Input Voltage V Minimum HIGH Level 4.5 OH Output Voltage 5.5 4.5 5.5 V Maximum LOW Level ...

Page 6

AC Operating Requirements for ACT Symbol Parameter t Setup Time, HIGH or LOW Hold Time, HIGH or LOW Pulse Width, HIGH W Note 10: Voltage Range 5.0 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body Package Number M20B 7 www.fairchildsemi.com ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide www.fairchildsemi.com Package Number M20D 8 ...

Page 9

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 9 www.fairchildsemi.com ...

Page 10

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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