74LVC373APW,112 NXP Semiconductors, 74LVC373APW,112 Datasheet - Page 11
![IC OCTAL D TRANSP LATCH 20TSSOP](/photos/6/52/65219/568-20-tssop_sot360-1_sml.jpg)
74LVC373APW,112
Manufacturer Part Number
74LVC373APW,112
Description
IC OCTAL D TRANSP LATCH 20TSSOP
Manufacturer
NXP Semiconductors
Series
74LVCr
Datasheet
1.74LVC373APW118.pdf
(20 pages)
Specifications of 74LVC373APW,112
Logic Type
D-Type Transparent Latch
Circuit
8:8
Output Type
Tri-State
Voltage - Supply
2.7 V ~ 3.6 V
Independent Circuits
1
Delay Time - Propagation
1.5ns
Current - Output High, Low
24mA, 24mA
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74LVC373APW
74LVC373APW
935218650112
74LVC373APW
935218650112
Philips Semiconductors
2003 May 19
handbook, full pagewidth
handbook, full pagewidth
Octal D-type transparent latch with
5 V tolerant inputs/outputs; 3-state
V
V
V
V
V
V
V
V
V
V
M
M
OL
M
M
X
X
Y
Y
OL
= V
= V
= V
= V
= 1.5 V at V
= 0.5V
= 0.5V
= 1.5 V at V
and V
and V
OL
OL
OH
OH
Fig.9 Latch Enable input (LE) pulse width, the latch enable input to output (Qn) propagation delays.
+ 0.1V
+ 0.3 V at V
CC
OH
CC
OH
0.1V
0.3 V at V
are the typical output voltage drop that occur with the output load.
are the typical output voltage drop that occur with the output load.
at V
at V
CC
CC
CC
CC
CC
CC
at V
at V
< 2.7 V.
2.7 V;
2.7 V;
CC
CC
2.7 V;
CC
CC
2.7 V;
2.7 V.
2.7 V;
2.7 V;
HIGH-to-OFF
OFF-to-HIGH
LOW-to-OFF
OFF-to-LOW
Qn output
Qn output
Qn output
LE input
OE input
GND
V OH
V OL
GND
GND
V OH
V I
V CC
V OL
Fig.10 3-state enable and disable times.
V I
enabled
V M
V M
output
t PLZ
t PHL
t PHZ
t W
V X
V M
11
V Y
disabled
output
t PLH
t PZL
t PZH
V M
V M
MNA885
output
enabled
MNA886
Product specification
74LVC373A