74LVT373WMX Fairchild Semiconductor, 74LVT373WMX Datasheet - Page 2
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74LVT373WMX
Manufacturer Part Number
74LVT373WMX
Description
IC LATCH TRANSP OCT 3ST 20SOIC
Manufacturer
Fairchild Semiconductor
Series
74LVTr
Datasheet
1.74LVT373MTC.pdf
(10 pages)
Specifications of 74LVT373WMX
Logic Type
D-Type Transparent Latch
Circuit
8:8
Output Type
Tri-State
Voltage - Supply
2.7 V ~ 3.6 V
Independent Circuits
1
Delay Time - Propagation
1.5ns
Current - Output High, Low
32mA, 64mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-SOIC (7.5mm Width)
Number Of Circuits
8
Logic Family
74LVT
Polarity
Non-Inverting
High Level Output Current
- 32 mA
Propagation Delay Time
5 ns at 2.7 V, 4.5 ns at 3.3 V
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Current
5 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
©1999 Fairchild Semiconductor Corporation
74LVT373, 74LVTH373 Rev. 1.5.0
Connection Diagram
Pin Description
Functional Description
The LVT373 and LVTH373 contain eight D-type latches
with 3-STATE standard outputs. When the Latch Enable
(LE) input is HIGH, data on the D
latches. In this condition the latches are transparent, i.e.,
a latch output will change state each time its D input
changes. When LE is LOW, the latches store the infor-
mation that was present on the D inputs a setup time
preceding the HIGH-to-LOW transition of LE. The
3-STATE standard outputs are controlled by the Output
Enable (OE) input. When OE is LOW, the standard out-
puts are in the 2-state mode. When OE is HIGH, the
standard outputs are in the high impedance mode but
this does not interfere with entering new data into the
latches.
D
LE
OE
O
Pin Names
0
0
–D
–O
7
7
Data Inputs
Latch Enable Input
Output Enable Input
3-STATE Latch Outputs
Description
n
inputs enters the
2
Logic Symbols
Truth Table
H
L
Z
X
O
of Latch Enable
0
LOW Voltage Level
High Impedance
Immaterial
HIGH Voltage Level
LE
H
H
X
L
Previous O
Inputs
OE
0
H
L
L
L
before HIGH-to-LOW transition
IEEE/IEC
D
X
H
X
L
n
Outputs
www.fairchildsemi.com
O
O
H
Z
L
n
0