74LVT373WMX Fairchild Semiconductor, 74LVT373WMX Datasheet - Page 7
![IC LATCH TRANSP OCT 3ST 20SOIC](/photos/7/6/70641/261-20-soicw_sml.jpg)
74LVT373WMX
Manufacturer Part Number
74LVT373WMX
Description
IC LATCH TRANSP OCT 3ST 20SOIC
Manufacturer
Fairchild Semiconductor
Series
74LVTr
Datasheet
1.74LVT373MTC.pdf
(10 pages)
Specifications of 74LVT373WMX
Logic Type
D-Type Transparent Latch
Circuit
8:8
Output Type
Tri-State
Voltage - Supply
2.7 V ~ 3.6 V
Independent Circuits
1
Delay Time - Propagation
1.5ns
Current - Output High, Low
32mA, 64mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-SOIC (7.5mm Width)
Number Of Circuits
8
Logic Family
74LVT
Polarity
Non-Inverting
High Level Output Current
- 32 mA
Propagation Delay Time
5 ns at 2.7 V, 4.5 ns at 3.3 V
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Current
5 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
©1999 Fairchild Semiconductor Corporation
74LVT373, 74LVTH373 Rev. 1.5.0
Physical Dimensions
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
10.65
10.00
INDICATOR
(R0.10)
PIN ONE
8°
0°
(R0.10)
7.60
7.40
B
Figure 1. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
2.65 MAX
1.27
0.40
(1.40)
20
1
SEATING PLANE
DETAIL A
0.75
0.25
SCALE: 2:1
0.35
0.51
0.25
13.00
12.60
11.43
X 45°
GAGE PLANE
0.25
M
C
B
A
1.27
0.30
0.10
11
10
NOTES: UNLESS OTHERWISE SPECIFIED
A
A) THIS PACKAGE CONFORMS TO JEDEC
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
D) CONFORMS TO ASME Y14.5M-1994
E) LANDPATTERN STANDARD: SOIC127P1030X265-20L
F) DRAWING FILENAME: MKT-M20BREV3
7
C
0.10 C
MS-013, VARIATION AC, ISSUE E
FLASH OR BURRS.
LAND PATTERN RECOMMENDATION
2.25
1.27
SEE DETAIL A
SEATING PLANE
0.65
www.fairchildsemi.com
0.33
0.20
9.50