74LVT573MTC Fairchild Semiconductor, 74LVT573MTC Datasheet

74LVT573MTC

Manufacturer Part Number

74LVT573MTC

Description

IC LATCH TRANSP OCT 3ST 20TSSOP

Manufacturer

Fairchild Semiconductor

Series

74LVTr

Datasheets

1.74LVT573WMX.pdf (11 pages)

2.74LVT573MTC.pdf (8 pages)

Specifications of 74LVT573MTC

Logic Type

D-Type Transparent Latch

Circuit

8:8

Output Type

Tri-State

Voltage - Supply

2.7 V ~ 3.6 V

Independent Circuits

Delay Time - Propagation

1.5ns

Current - Output High, Low

32mA, 64mA

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

20-TSSOP

Number Of Circuits

Logic Family

74LVT

Polarity

Non-Inverting

High Level Output Current

- 32 mA

Low Level Output Current

64 mA

Propagation Delay Time

4.9 ns at 2.7 V, 4.4 ns at 3.3 V

Supply Voltage (max)

3.6 V

Supply Voltage (min)

2.7 V

Maximum Operating Temperature

+ 85 C

Minimum Operating Temperature

- 40 C

Mounting Style

SMD/SMT

Supply Current

5 mA

Latch Type

Transparent

Output Current

64mA

Propagation Delay

4.1ns

No. Of Bits

Ic Output Type

Tri State Non Inverted

Supply Voltage Range

2.7V To 3.6V

Logic Case Style

TSSOP

No. Of Pins

Rohs Compliant

Yes

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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74LVT573WM

74LVT573SJ

74LVT573MSA

74LVT573MTC

74LVT573MTCX_NL

(Note 1)

74LVTH573WM

74LVTH573SJ

74LVTH573MSA

74LVTH573MTC

74LVTH573MTCX_NL

(Note 1)

74LVT573 • 74LVTH573

Low Voltage Octal Transparent Latch

with 3-STATE Outputs

General Description

The LVT573 and LVTH573 consist of eight latches with

3-STATE outputs for bus organized system applications.

The latches appear transparent to the data when Latch

Enable (LE) is HIGH. When LE is low, the data satisfying

the input timing requirements is latched. Data appears on

the bus when the Output Enable (OE) is LOW. When OE is

HIGH, the bus output is in the high impedance state.

The LVTH573 data inputs include bushold, eliminating the

need for external pull-up resistors to hold unused inputs.

These octal latches are designed for low-voltage (3.3V)

interface to a 5V environment. The LVT573 and LVTH573

are fabricated with an advanced BiCMOS technology to

achieve high speed operation similar to 5V ABT while

maintaining a low power dissipation.

Ordering Code:

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Pb-Free package per JEDEC J-STD-020B.

Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.

Order Number

applications, but with the capability to provide a TTL

Package

Number

MSA20

MTC20

MSA20

MTC20

M20D

M20B

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

DS012450

Features

Input and output interface capability to systems at

5V V

Bushold data inputs eliminate the need for external

pull-up resistors to hold unused inputs (74LVTH573),

also available without bushold feature (74LVT573)

Live insertion/extraction permitted

Power Up/Down high impedance provides glitch-free

bus loading

Outputs source/sink

Functionally compatible with the 74 series 573

Latch-up performance exceeds 500 mA

ESD performance:

Human-body model

Machine model

Charged-device model

Package Description

200V

32 mA/

2000V

1000V

March 1999

Revised March 2005

64 mA

www.fairchildsemi.com

Related parts for 74LVT573MTC

74LVT573MTC Summary of contents

Page 1

... MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 74LVT573MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74LVT573MTCX_NL MTC20 Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm (Note 1) Wide 74LVTH573WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" ...

Page 2

Logic Symbols IEEE/IEC Connection Diagram Functional Description The LVT573 and LVTH573 contain eight D-type latches with 3-STATE standard outputs. When the Latch Enable (LE) input is HIGH, data on the D inputs enters the latches. In this condition the latches ...

Page 3

Absolute Maximum Ratings Symbol Parameter V Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Current Supply Current ...

Page 4

DC Electrical Characteristics Symbol Parameter I 3-STATE Output Leakage Current OZH I Power Supply Current CCH I Power Supply Current CCL I Power Supply Current CCZ I Power Supply Current CCZ ' I Increase in Power Supply Current ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide www.fairchildsemi.com Package Number M20D 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package Number MSA20 7 www.fairchildsemi.com ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

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