74LVT573MTC Fairchild Semiconductor, 74LVT573MTC Datasheet - Page 4

IC LATCH TRANSP OCT 3ST 20TSSOP

74LVT573MTC

Manufacturer Part Number
74LVT573MTC
Description
IC LATCH TRANSP OCT 3ST 20TSSOP
Manufacturer
Fairchild Semiconductor
Series
74LVTr
Datasheets

Specifications of 74LVT573MTC

Logic Type
D-Type Transparent Latch
Circuit
8:8
Output Type
Tri-State
Voltage - Supply
2.7 V ~ 3.6 V
Independent Circuits
1
Delay Time - Propagation
1.5ns
Current - Output High, Low
32mA, 64mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP
Number Of Circuits
8
Logic Family
74LVT
Polarity
Non-Inverting
High Level Output Current
- 32 mA
Low Level Output Current
64 mA
Propagation Delay Time
4.9 ns at 2.7 V, 4.4 ns at 3.3 V
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Current
5 mA
Latch Type
Transparent
Output Current
64mA
Propagation Delay
4.1ns
No. Of Bits
8
Ic Output Type
Tri State Non Inverted
Supply Voltage Range
2.7V To 3.6V
Logic Case Style
TSSOP
No. Of Pins
20
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
www.fairchildsemi.com
V
V
t
t
t
t
t
t
t
t
t
t
t
t
t
C
C
I
I
I
I
I
'
PHL
PLH
PHL
PLH
PZL
PZH
PLZ
PHZ
S
H
W
OSHL
OSLH
DC Electrical Characteristics
Note 4: All typical values are at V
Note 5: Applies to bushold versions only (74LVTH573).
Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 8: This is the increase in supply current for each input that is at the specified voltage level rather than V
Dynamic Switching Characteristics
Note 9: Characterized in SOIC package. Guaranteed parameter, but not tested.
Note 10: Max number of outputs defined as (n). n
AC Electrical Characteristics
Note 11: All typical values are at V
Note 12: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
Capacitance
Note 13: Capacitance is measured at frequency f
OZH
CCH
CCL
CCZ
CCZ
OLP
OLV
IN
OUT
I
Symbol
CC
Symbol
Symbol
Symbol


Quiet Output Maximum Dynamic V
Quiet Output Minimum Dynamic V
Propagation Delay
D
Propagation Delay
LE to O
Output Enable Time
Output Disable Time
Setup Time, D
Hold Time, D
LE Pulse Width
Output to Output Skew (Note 12)
Input Capacitance
Output Capacitance
3-STATE Output Leakage Current
Power Supply Current
Power Supply Current
Power Supply Current
Power Supply Current
Increase in Power Supply Current
(Note 8)
n
to O
n
n
(Note 13)
n
Parameter
n
to LE
Parameter
to LE
CC
Parameter
Parameter
CC
3.3V, T
3.3V, T
A
A
25

25
1 data inputs are driven 0V to 3V. Output under test held LOW.
1 MHz, per MIL-STD-883, Method 3012.
q
OL
C.
q
OL
C.
V
(Continued)
(V)
3.3
3.3
CC
V
V
CC
CC
V
3.6
3.6
3.6
3.6
3.6
3.6
(V)
CC
Min
1.5
1.5
1.9
1.9
1.5
1.5
2.0
2.0
0.7
1.5
3.0
Open, V
3.0V, V
Min
(Note 9)
4
O
V
Min
I
CC
Conditions
T
0V or V
0V or V
(Note 11)
A
T
3.3V
A
Typ


Typ
OSHL
0.8
(Note 4)
40
0.8
25
CC
CC
Typ
r
q
C
C to
q
) or LOW-to-HIGH (t
T
0.3V
C
L
A

50 pF, R

85
40
Max
q
Max
Max
0.19
0.19
0.19
q
4.4
4.1
4.4
4.4
5.1
5.1
4.6
4.9
1.0
1.0
C
0.2
10
C to
5
CC
L

or GND.
85
500
OSLH
Units
Units
q
C
mA
mA
mA
mA
mA
P
V
V
:
A
).
Min
1.5
1.5
1.9
1.9
1.5
1.5
2.0
2.0
0.6
1.7
3.0
Typical
V
Outputs HIGH
Outputs LOW
Outputs Disabled
V
Outputs Disabled
One Input at V
Other Inputs at V
4
6
V
C
CC
CC
CC
L

d
50 pF, R
V
V
2.7V
O
O
Conditions
d
d
Conditions
(Note 10)
(Note 10)
Max
5.5V
5.5V,
4.9
4.7
4.9
5.0
6.6
5.9
4.9
5.5
1.0
1.0
CC
L
CC

500
Units
0.6V
or GND
pF
pF
:
Units
ns
ns
ns
ns
ns
ns
ns
ns

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