74LVT573MTC Fairchild Semiconductor, 74LVT573MTC Datasheet - Page 2

• Manufacturer Part Number: 74LVT573MTC
• Description: IC LATCH TRANSP OCT 3ST 20TSSOP
• Manufacturer: Fairchild Semiconductor
• Series: 74LVTr

Specifications of 74LVT573MTC

• Logic Type: D-Type Transparent Latch
• Circuit: 8:8
• Output Type: Tri-State
• Voltage - Supply: 2.7 V ~ 3.6 V
• Independent Circuits: 1
• Delay Time - Propagation: 1.5ns
• Current - Output High, Low: 32mA, 64mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Number Of Circuits: 8
• Logic Family: 74LVT
• Polarity: Non-Inverting
• High Level Output Current: - 32 mA
• Low Level Output Current: 64 mA
• Propagation Delay Time: 4.9 ns at 2.7 V, 4.4 ns at 3.3 V
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Current: 5 mA
• Latch Type: Transparent
• Output Current: 64mA
• Propagation Delay: 4.1ns
• No. Of Bits: 8
• Ic Output Type: Tri State Non Inverted
• Supply Voltage Range: 2.7V To 3.6V
• Logic Case Style: TSSOP
• No. Of Pins: 20
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

©1999 Fairchild Semiconductor Corporation
74LVT573, 74LVTH573 Rev. 1.7.0
Connection Diagram
Pin Description
Functional Description
The LVT573 and LVTH573 contain eight D-type latches
with 3-STATE standard outputs. When the Latch Enable
(LE) input is HIGH, data on the D
latches. In this condition the latches are transparent, i.e.,
a latch output will change state each time its D-type input
changes. When LE is LOW, the latches store the infor-
mation that was present on the D-type inputs a setup
time preceding the HIGH-to-LOW transition of LE. The
3-STATE standard outputs are controlled by the Output
Enable (OE) input. When OE is LOW, the standard out-
puts are in the 2-state mode. When OE is HIGH, the
standard outputs are in the high impedance mode but
this does not interfere with entering new data into the
latches.
D
LE
OE
O
Pin Names
0
0
–D
–O
7
7
Data Inputs
Latch Enable Input
Output Enable Input
3-STATE Latch Outputs
Description
n
inputs enters the
2
Logic Symbols
Truth Table
H
L
Z
X
O
of Latch Enable
0
LOW Voltage Level
High Impedance
Immaterial
HIGH Voltage Level
LE
Previous O
X
H
H
L
Inputs
0
OE
before HIGH to LOW transition
H
L
L
L
IEEE/IEC
D
X
H
X
L
n
Outputs
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O
O
H
Z
L
n
0