74LV373D,112 NXP Semiconductors, 74LV373D,112 Datasheet - Page 2

• Manufacturer Part Number: 74LV373D,112
• Description: IC OCTAL D TRANSP LATCH 20SOIC
• Manufacturer: NXP Semiconductors
• Series: 74LVr

Specifications of 74LV373D,112

• Logic Type: D-Type Transparent Latch
• Circuit: 8:8
• Output Type: Tri-State
• Voltage - Supply: 1 V ~ 5.5 V
• Independent Circuits: 1
• Delay Time - Propagation: 20ns
• Current - Output High, Low: 16mA, 16mA
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74LV373D; 74LV373D; 935063250112

1. C
2. The condition is V
Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
GND = 0V; T
NOTES:
ORDERING AND PACKAGE INFORMATION
PIN DESCRIPTION
t
C
C
20-Pin Plastic DIL
20-Pin Plastic SO
20-Pin Plastic SSOP Type II
20-Pin Plastic TSSOP Type I
PIN NUMBER
1998 Jun 10
PHL
2, 5, 6, 9, 12,
3, 4, 7, 8, 13,
Wide operating voltage: 1.0 to 5.5V
Optimized for Low Voltage applications: 1.0V to 3.6V
Accepts TTL input levels between V
Typical V
T
Typical V
T
Common 3-State output enable input
Output capability: bus driver
I
Octal D-type transparent latch (3-State)
I
PD
CC
P
f
f
amb
amb
15, 16, 19
14, 17, 18
i
o
PD
D
= input frequency in MHz; C
/t
= output frequency in MHz; V
(C
category: MSI
PLH
= C
10
20
SYMBOL
11
= 25 C
= 25 C
1
L
is used to determine the dynamic power dissipation (P
PACKAGES
PD
OLP
OHV
amb
V
CC
(output ground bounce) < 0.8V at V
(output V
V
2
= 25 C; t
CC
SYMBOL
Q
D
2
GND
f
I
V
o
OE
0
0
x f
LE
= GND to V
) = sum of the outputs.
–Q
–D
CC
i
OH
r
Propagation delay
D
LE to Q
Input capacitance
Power dissipation capacitance per latch
) (C
7
7
= t
n
undershoot) > 2V at V
to Q
f
v2.5 ns
Output enabled input (active LOW)
3-State latch outputs
Data inputs
Ground (0V)
Latch enable input (active HIGH)
Positive supply voltage
L
L
n
n
TEMPERATURE RANGE
CC.
= output load capacity in pF;
CC
V
CC
= supply voltage in V;
–40 C to +125 C
–40 C to +125 C
–40 C to +125 C
–40 C to +125 C
CC
PARAMETER
= 2.7V and V
2
FUNCTION
f
o
) where:
CC
CC
= 3.3V,
= 3.3V,
CC
= 3.6V
D
in W)
OUTSIDE NORTH AMERICA
C
V
Notes 1, 2
L
CC
2
= 15pF
74LV373 PW
= 3.3V
74LV373 DB
74LV373 N
74LV373 D
DESCRIPTION
The 74LV373 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT373.
The 74LV373 is an octal D-type transparent latch featuring separate
D-type inputs for each latch and 3-State outputs for bus oriented
applications. A latch enable (LE) input and an output enable (OE)
input are common to all internal latches.
The ‘373’ consists of eight D-type transparent latches with 3-State
true outputs. When LE is HIGH, data at the Dn inputs enters the
latches. In this condition the latches are transparent, i.e., a latch
output will change each time its corresponding D-input changes.
When LE is LOW the latches store the information that was present
at the D-inputs a set-up time preceding the HIGH-to-LOW transition
of LE. When OE is LOW, the contents of the eight latches are
available at the outputs. When OE is HIGH, the outputs go to the
high impedance OFF-state. Operation of the OE input does not
affect the state of the latches.
The ‘373’ is functionally identical to the ‘573’, but the ‘573’ has a
different pin arrangement.
CONDITIONS
NORTH AMERICA
74LV373PW DH
74LV373 DB
74LV373 N
74LV373 D
TYPICAL
3.5
10
12
22
Product specification
74LV373
853–1934 19545
PKG. DWG. #
SOT146-1
SOT163-1
SOT339-1
SOT360-1
UNIT
pF
pF
ns