74AUP1G373GF,132 NXP Semiconductors, 74AUP1G373GF,132 Datasheet - Page 13

• Manufacturer Part Number: 74AUP1G373GF,132
• Description: IC LATCH D-TYPE 6-XSON
• Manufacturer: NXP Semiconductors
• Series: 74AUPr

Specifications of 74AUP1G373GF,132

• Logic Type: D-Type Transparent Latch
• Package / Case: 6-XSON, SOT891
• Circuit: 1:1
• Output Type: Tri-State
• Voltage - Supply: 0.8 V ~ 3.6 V
• Independent Circuits: 1
• Delay Time - Propagation: 2.5ns
• Current - Output High, Low: 4mA, 4mA
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Circuits: 1
• Logic Family: 74AUP
• Polarity: Non-Inverting
• High Level Output Current: - 4 mA
• Low Level Output Current: 4 mA
• Propagation Delay Time: 22.1 ns at 1.1 V to 1.3 V, 12.3 ns at 1.4 V to 1.6 V
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 0.8 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Current: 50 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 74AUP1G373GF-H; 74AUP1G373GF-H; 935281332132

NXP Semiconductors
Table 8.
Voltages are referenced to GND (ground = 0 V); for test circuit see
[1]
[2]
[3]
[4]
[5]
[6]
12. Waveforms
74AUP1G373
Product data sheet
Symbol Parameter
C
Fig 7.
PD
All typical values are measured at nominal V
t
t
t
All specified values are the average typical values over all stated loads.
C
P
f
f
C
V
(C
N = number of inputs switching.
pd
en
dis
i
o
D
CC
PD
= input frequency in MHz;
L
= output frequency in MHz;
is the same as t
is the same as t
= output load capacitance in pF;
= C
is the same as t
L
is used to determine the dynamic power dissipation (P
= supply voltage in V;
 V
power
dissipation
capacitance
Measurement points are given in
Logic levels: V
The data input (D) to output (Q) propagation delays
PD
Dynamic characteristics
CC
 V
2
 f
CC
o
2
) = sum of the outputs;
 f
PLH
PZH
PHZ
i
 N + (C
OL
Conditions
f
output enabled
i
and t
and t
and t
= 1 MHz; V
and V
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
PHL
PZL
PLZ
= 0.8 V
= 1.1 V to 1.3 V
= 1.4 V to 1.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 3.0 V to 3.6 V
OH
L
.
.
.
 V
are typical output voltage levels that occur with the output load.
CC
I
Q output
D input
= GND to V
2
…continued
 f
Table
o
All information provided in this document is subject to legal disclaimers.
) where:
CC
GND
V
9.
V
.
OH
OL
V
I
CC
Rev. 4 — 15 July 2010
[5][6]
D
V
in W).
M
V
Min Typ
M
t
-
-
-
-
-
-
PHL
Figure
25 C
2.0
2.0
2.0
2.1
2.4
2.8
[1]
Low-power D-type transparent latch; 3-state
11.
Max
-
-
-
-
-
-
001aae253
t
PLH
(85 C)
Min
-
-
-
-
-
-
40 C to +125 C
(85 C)
Max
74AUP1G373
-
-
-
-
-
-
(125 C)
Min
-
-
-
-
-
-
© NXP B.V. 2010. All rights reserved.
(125 C)
Max
-
-
-
-
-
-
13 of 25
Unit
pF
pF
pF
pF
pF
pF