74LVC841AD,118 NXP Semiconductors, 74LVC841AD,118 Datasheet

74LVC841AD,118

Manufacturer Part Number

74LVC841AD,118

Description

IC 10BIT TRANSP LATCH 24SOIC

Manufacturer

NXP Semiconductors

Series

74LVCr

Datasheet

1.74LVC841AD112.pdf (21 pages)

Specifications of 74LVC841AD,118

Logic Type

D-Type Transparent Latch

Circuit

10:10

Output Type

Tri-State

Voltage - Supply

2.7 V ~ 3.6 V

Independent Circuits

Delay Time - Propagation

1.5ns

Current - Output High, Low

24mA, 24mA

Operating Temperature

-40°C ~ 125°C

Mounting Type

Surface Mount

Package / Case

24-SOIC (7.5mm Width)

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Other names

74LVC841AD-T
74LVC841AD-T
935262141118

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1. General description

2. Features

The 74LVC841A is a high performance, low-power, low-voltage Si-gate CMOS device and

superior to most advanced CMOS compatible TTL families.

Inputs can be driven from either 3.3 V or 5 V devices. In 3-state operation, outputs can

handle 5 V. This feature allows the use of these devices as translators in a mixed

3.3 V and 5 V environment.

The 74LVC841A is a 10-bit transparent latch featuring separate D-type inputs for each

latch and 3-state outputs for bus-oriented applications. A latch enable (pin LE) input and

an output enable (pin OE) input are common to all internal latches. The 74LVC841A

consists of ten transparent latches with 3-state true outputs. When pin LE is HIGH, data at

the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch

output will change each time its corresponding D-input changes. When pin LE is LOW the

latches store the information that was present at the D-inputs a set-up time preceding the

HIGH-to-LOW transition of pin LE. When pin OE is LOW, the contents of the ten latches

are available at the outputs. When pin OE is HIGH, the outputs go to the high-impedance

OFF-state. Operation of the pin OE input does not affect the state of the latches.

74LVC841A

10-bit transparent latch with 5 V tolerant inputs/outputs;

3-state

Rev. 03 — 24 May 2004

5 V tolerant inputs/outputs; for interfacing with 5 V logic

Wide supply voltage range from 1.2 V to 3.6 V

Inputs accept voltages up to 5.5 V

CMOS low power consumption

Direct interface with TTL levels

Flow-through pin-out architecture

Complies with JEDEC standard JESD8B/JESD36

ESD protection:

Speciﬁed from 40 C to +85 C and 40 C to +125 C.

HBM EIA/JESD22-A114-B exceeds 2000 V

MM EIA/JESD22-A115-A exceeds 200 V.

Product data sheet

Related parts for 74LVC841AD,118

74LVC841AD,118 Summary of contents

Page 1

V tolerant inputs/outputs; 3-state Rev. 03 — 24 May 2004 1. General description The 74LVC841A is a high performance, low-power, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs ...

Page 2

Philips Semiconductors 3. Quick reference data Table 1: GND = Symbol PHL PLH PZH PZL PHZ PLZ [ ...

Page 3

Philips Semiconductors 5. Functional diagram Fig 1. Functional diagram. Fig 2. Logic symbol. 9397 750 13129 Product data sheet 10-bit transparant latch with 5 V tolerant inputs/outputs; 3-state Fig 3. IEC Logic symbol. Rev. 03 — 24 May 2004 74LVC841A ...

Page 4

Philips Semiconductors LE OE Fig 4. Logic diagram 9397 750 13129 Product data sheet 10-bit transparant latch with 5 V tolerant inputs/outputs; 3-state LATCH LATCH ...

Page 5

Philips Semiconductors 6. Pinning information 6.1 Pinning Fig 5. Pin conﬁguration for SO24 and 6.2 Pin description Table 3: Pin 9397 750 13129 Product data ...

Page 6

Philips Semiconductors Table 3: Pin Functional description 7.1 Function table Table 4: Operating mode Enable and read register (transparent mode) Latch and read register Latch register and disable outputs Hold ...

Page 7

Philips Semiconductors Table 5: Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V output voltage O I output source or sink current O I ...

Page 8

Philips Semiconductors Table 7: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter V HIGH-level output OH voltage V LOW-level output OL voltage I input leakage current LI I 3-state output OZ ...

Page 9

Philips Semiconductors Table 7: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter I power-off leakage off supply I quiescent supply CC current I additional quiescent CC supply current per pin [1] ...

Page 10

Philips Semiconductors Table 8: Dynamic characteristics GND = 2 Symbol Parameter t set-up time hold time ...

Page 11

Philips Semiconductors Table 8: Dynamic characteristics GND = 2 Symbol Parameter t hold time skew sk(0) [1] All typical values are ...

Page 12

Philips Semiconductors Fig 8. Latch enable input (LE) pulse width, the latch enable input to output (Qn) Fig 9. Data setup and hold times for the Dn input to the LE input. 9397 750 13129 Product data sheet 10-bit transparant ...

Page 13

Philips Semiconductors Fig 10. 3-state enable and disable times. 9397 750 13129 Product data sheet 10-bit transparant latch with 5 V tolerant inputs/outputs; 3-state input V M GND t PLZ output LOW-to-OFF OFF-to-LOW V ...

Page 14

Philips Semiconductors Fig 11. Load circuitry for switching times. Table 9: Supply voltage Input V CC 1.2 V 2 3.6 V [1] The circuit performs better when R 9397 750 13129 Product data sheet 10-bit transparant ...

Page 15

Philips Semiconductors 13. Package outline SO24: plastic small outline package; 24 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT ...

Page 16

Philips Semiconductors SSOP24: plastic shrink small outline package; 24 leads; body width 5 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. ...

Page 17

Philips Semiconductors TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm ...

Page 18

Philips Semiconductors DHVQFN24: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm terminal 1 index area terminal 1 index area ...

Page 19

Philips Semiconductors 14. Revision history Table 10: Revision history Document ID Release date 74LVC841A_3 20040524 • Modiﬁcations: The format of this data sheet has been redesigned to comply with the current presentation and information standard of Phillips Semiconductors. • Addition ...

Page 20

Philips Semiconductors 15. Data sheet status [1] Level Data sheet status Product status I Objective data Development II Preliminary data Qualiﬁcation III Product data Production [1] Please consult the most recently issued data sheet before initiating or completing a design. ...

Page 21

Philips Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . 1 2 Features ...

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