74ABT16373BDGG,518 NXP Semiconductors, 74ABT16373BDGG,518 Datasheet - Page 2
![IC 16BIT D TYPE LATCH 48TSSOP](/photos/6/50/65054/568-48-tssop_sot480-1_sml.jpg)
74ABT16373BDGG,518
Manufacturer Part Number
74ABT16373BDGG,518
Description
IC 16BIT D TYPE LATCH 48TSSOP
Manufacturer
NXP Semiconductors
Series
74ABTr
Datasheet
1.74ABT16373BDGG118.pdf
(11 pages)
Specifications of 74ABT16373BDGG,518
Logic Type
D-Type Transparent Latch
Circuit
8:8
Output Type
Tri-State
Voltage - Supply
4.5 V ~ 5.5 V
Independent Circuits
2
Delay Time - Propagation
2ns
Current - Output High, Low
32mA, 64mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74ABT16373BDG-T
74ABT16373BDG-T
935203330518
74ABT16373BDG-T
935203330518
The data on each set of D inputs are transferred to the latch outputs
FEATURES
DESCRIPTION
The 74ABT16373B high-performance BiCMOS device combines
low static and dynamic power dissipation with high speed and high
output drive.
The 74ABT16373B device is a dual octal transparent latch coupled
to two sets of eight 3-State output buffers. The two sections of the
device are controlled independently by Enable (nE) and Output
Enable (nOE) control gates.
when the Latch Enable (nE) input is HIGH. The latch remains
transparent to the data inputs while nE is HIGH, and stores the data
that is present one set-up time before the HIGH-to-LOW enable
transition.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. Each
active-LOW Output Enable (nOE) controls eight 3-State buffers
independent of the latch operation.
When nOE is LOW, the latched or transparent data appears at the
outputs. When nOE is HIGH, the outputs are in the high-impedance
“OFF” state, which means they will neither drive nor load the bus.
QUICK REFERENCE DATA
ORDERING INFORMATION
T
Philips Semiconductors
amb
Type number
74ABT16373BDL
74ABT16373BDGG
2004 Feb 27
SYMBOL
16-bit transparent latch
Multiple V
Power-up 3-State
Live insertion/extraction permitted
Power-up reset
3-State output buffers
Output capability: +64 mA/–32 mA
I
Latch-up protection exceeds 500 mA per JEDEC Std 17
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
16-bit transparent latch (3-State)
CCL
C
I
t
t
I
C
PLH
PHL
CCZ
CCL
= –40 C to +85 C
OUT
IN
–19 mA maximum
CC
and GND pins minimize switching noise
Propagation delay
Dn to Qn
Input capacitance
Output capacitance
Quiescent supply current
Quiescent supply current
Package
Name
SSOP48
TSSOP48
PARAMETER
Description
plastic shrink small outline package; 48 leads; body width 7.5 mm
plastic thin shrink small outline package; 48 leads; body width 6.1 mm
2
PIN CONFIGURATION
Outputs disabled; V
T
Outputs low; V
V
amb
C
O
L
= 0 V or V
= 50 pF; V
V
CONDITIONS
= 25 C; GND = 0 V
I
= 0 V or V
CC
CC
GND
GND
GND
GND
CC
1OE
2OE
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
V
V
; 3-State
CC
CC
CC
CC
= 5.5 V
= 5 V
= 5.5 V
10
12
13
14
15
16
17
18
19
20
21
22
23
24
11
1
2
3
4
5
6
7
8
9
74ABT16373B
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SA00379
TYPICAL
1E
1D0
1D1
GND
1D2
1D3
V
1D4
1D5
GND
1D6
1D7
2D0
2D1
GND
2D2
2D3
V
2D4
2D5
GND
2D6
2D7
2E
500
CC
CC
2.5
2.0
4
7
8
Version
SOT370-1
SOT362-1
Product data
UNIT
mA
pF
pF
ns
A