GDS1110AB Intel Corporation, GDS1110AB Datasheet

GDS1110AB

Manufacturer Part Number

GDS1110AB

Description

Manufacturer

Intel Corporation

Datasheets

1.GDS1110BB.pdf (10 pages)

2.GDS1110AB.pdf (10 pages)

3.GDS1110AB.pdf (72 pages)

Specifications of GDS1110AB

Case

BGA

Date_code

00+

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

GDS1110AB

Manufacturer:

ABOV

Quantity:

5 309

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Download datasheet (81Kb)

Intel

Microprocessor

Product Features

High performance

Low power (normal mode)

Integrated clock generation

Power-management features

Big and little endian operating modes

3.3-V I/O interface

— 150 Dhrystone 2.1 MIPS @ 133 MHz

— 235 Dhrystone 2.1 MIPS @ 206 MHz

— <240 mW @1.55 V/133 MHz

— <400 mW @1.75 V/206 MHz

— Internal phase-locked loop (PLL)

— 3.686-MHz oscillator

— 32.768-kHz oscillator

— Normal (full-on) mode

— Idle (power-down) mode

— Sleep (power-down) mode

StrongARM* SA-1110

The Intel

optimized for meeting portable and embedded application requirements.

The SA-1110 incorporates a 32-bit StrongARM RISC processor capable of

running at up to 206 MHz. The SA-1110 has a large instruction and data

cache, memory-management unit (MMU), and read/write buffers. The

SA-1110 memory bus interfaces to many device types including

synchronous DRAM (SDRAM), synchronous mask ROM (SMROM), and

SRAM-like variable latency I/O devices with a shared data ready signal. In

addition, the SA-1110 provides system support logic, multiple serial

communication channels, a color/gray scale LCD controller, PCMCIA

support for up to two sockets, and general-purpose I/O ports.

†

Power dissipation, particularly in idle mode, is strongly dependent on the details of the

system design

StrongARM SA-1110 Microprocessor (SA-1110) is a device

†

Memory bus

32-way set-associative caches

32-entry MMUs

Write buffer

Read buffer

256 mini-ball grid array (mBGA)

— Interfaces to ROM, synchronous mask

— Supports two PCMCIA sockets

— 16 Kbyte instruction cache

— 8 Kbyte write-back data cache

— Maps 4 Kbyte, 8 Kbyte, or 1 Mbyte

— 8-entry, between 1 and 16 bytes each

— 4-entry, 1, 4, or 8 words

ROM (SMROM), Flash, SRAM,

SRAM-like variable latency I/O,

DRAM, and synchronous DRAM

(SDRAM)

Brief Datasheet

Order Number:

278241-005

April 2000

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