74LV123DB,112 NXP Semiconductors, 74LV123DB,112 Datasheet

IC DUAL RETRIG MULTIVIB 16SSOP

74LV123DB,112

Manufacturer Part Number
74LV123DB,112
Description
IC DUAL RETRIG MULTIVIB 16SSOP
Manufacturer
NXP Semiconductors
Series
74LVr
Datasheet

Specifications of 74LV123DB,112

Logic Type
Monostable
Independent Circuits
2
Schmitt Trigger Input
Yes
Propagation Delay
14ns
Current - Output High, Low
12mA, 12mA
Voltage - Supply
1 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
16-SSOP
Logic Family
LV
High Level Output Current
-12mA
Low Level Output Current
12mA
Number Of Elements
2
Operating Temperature Classification
Automotive
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (typ)
3.3V
Operating Temperature (min)
-40C
Operating Temperature (max)
125C
Technology
CMOS
Abs. Propagation Delay Time
92ns
Operating Supply Voltage (min)
1V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74LV123DB
74LV123DB
935210260112
1. General description
2. Features
The 74LV123 is a low-voltage Si-gate CMOS device and is pin and function compatible
with the 74HC123; 74HCT123. It is a dual retriggerable monostable multivibrator which
uses three methods to control the output pulse width:
Schmitt-trigger action in the nA and nB inputs makes the circuit highly tolerant of slower
input rise and fall times.
1. The basic pulse time is programmed by the selection of an external resistor (R
2. Once triggered, the basic output pulse width may be extended by retriggering the
3. Alternatively, an output delay can be terminated at any time by a LOW-going edge on
74LV123
Dual retriggerable monostable multivibrator with reset
Rev. 05 — 8 November 2007
Optimized for low-voltage applications: 1.0 V to 5.5 V
Accepts TTL input levels between V
Typical output ground bounce: < 0.8 V at V
Typical HIGH-level output voltage (V
T
DC triggered from active HIGH or active LOW inputs
Retriggerable for very long pulses up to 100 % duty factor
Direct reset terminates output pulses
Schmitt-trigger action on all inputs except for the reset input
and capacitor (C
gated active LOW-going edge input (nA) or the active HIGH-going edge input (nB). By
repeating this process, the output pulse period (nQ = HIGH, nQ = LOW) can be made
as long as desired (see
input nRD, which also inhibits the triggering (see
amb
= 25 C
EXT
). These are normally connected as shown in
Figure
12).
CC
OH
) undershoot: > 2 V at V
= 2.7 V and V
CC
= 3.3 V and T
Figure
CC
= 3.6 V
13).
amb
CC
= 25 C
Product data sheet
= 3.3 V and
Figure
9.
EXT
)

Related parts for 74LV123DB,112

74LV123DB,112 Summary of contents

Page 1

Dual retriggerable monostable multivibrator with reset Rev. 05 — 8 November 2007 1. General description The 74LV123 is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC123; 74HCT123 dual retriggerable monostable ...

Page 2

... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74LV123N +125 C 74LV123D +125 C 74LV123DB +125 C 74LV123PW +125 C 74LV123BQ +125 C 4. Functional diagram 1RD 3 2RD 11 Fig 1. Logic symbol 74LV123_5 Product data sheet Dual retriggerable monostable multivibrator with reset ...

Page 3

... NXP Semiconductors Fig 3. Functional diagram 74LV123_5 Product data sheet Dual retriggerable monostable multivibrator with reset 1RD 2RD Rev. 05 — 8 November 2007 14 1CEXT 15 1REXT/CEXT 2CEXT 7 2REXT/CEXT 001aaa610 © NXP B.V. 2007. All rights reserved. 74LV123 ...

Page 4

... NXP Semiconductors Fig 4. Logic diagram 74LV123_5 Product data sheet Dual retriggerable monostable multivibrator with reset Rev. 05 — 8 November 2007 74LV123 nREXT/CEXT V CC © NXP B.V. 2007. All rights reserved 001aae524 ...

Page 5

... NXP Semiconductors 5. Pinning information 5.1 Pinning 2CEXT 2REXT/CEXT Fig 5. Pin configuration for DIP16, SO16, 5.2 Pin description Table 2. Symbol 1A 1B 1RD 1Q 2Q 2CEXT 2REXT/CEXT GND 2A 2B 2RD 2Q 1Q 1CEXT 1REXT/CEXT V CC 74LV123_5 Product data sheet Dual retriggerable monostable multivibrator with reset ...

Page 6

... NXP Semiconductors 6. Functional description [1] Table 3. Function table Input nRD [ HIGH voltage level LOW voltage level don’t care; = LOW-to-HIGH transition; = HIGH-to-LOW transition; = one HIGH level output pulse = one LOW level output pulse [2] If the monostable multivibrator was triggered before this condition was established, the pulse will continue as programmed. ...

Page 7

... NXP Semiconductors 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC I input clamping current IK I output clamping current OK I output current O I supply current CC I ground current ...

Page 8

... NXP Semiconductors 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter +85 C amb V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current I I supply current ...

Page 9

... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current I I supply current CC I additional supply current CC [1] All typical values are measured at T 74LV123_5 ...

Page 10

... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 2.5 ns; for test circuit see r f Symbol Parameter Conditions Propagation delay; see Figure 7 t propagation delay nRD, nA and nRD to nQ (reset Inputs nA, nB and nRD; see Figure 7 t pulse width nA = LOW HIGH nRD = LOW; see ...

Page 11

... NXP Semiconductors Table 7. Dynamic characteristics GND = 2.5 ns; for test circuit see r f Symbol Parameter Conditions Outputs LOW and nQ = HIGH, see t pulse width C W EXT EXT External components R external see EXT resistance external see EXT capacitance Dynamic power dissipation C power dissipation V PD ...

Page 12

... NXP Semiconductors 11. Waveforms V nB input M (nA LOW input (nB HIGH) nRD input t PLH nQ output output PHL Measurement points are given in Fig 7. Propagation delays from inputs (nA, nB, nRD) to outputs (nQ, nQ) Table 8. Measurement points V CC 2.7 V < 2.7 V Test data is given in Table 9. Definitions for test circuit Load resistance ...

Page 13

... NXP Semiconductors Table 9. Supply voltage V CC < 2 3.6 V 4.5 V 12. Application information 12.1 Timing components 12.1.1 Basic timing The basic output pulse width is essentially determined by the values of the external timing components R (1) For minimum noise generation it is recommended to ground pins 6 (2CEXT) and 14 (1CEXT) Fig 9 ...

Page 14

... NXP Semiconductors 0.8 'K' factor 0.6 0 100 k EXT EXT Fig 10. Typical ‘K’ factor as a function of V 12.1.2 Retrigger timing The time to retrigger the monostable multivibrator depends on the values The output pulse width will only be extended when the time between the active EXT going edges of the trigger pulses meets the minimum retrigger time ...

Page 15

... NXP Semiconductors 12.1.3 Reset timing Fig 13. Output pulse control using reset input nRD 12.2 Power considerations 12.2.1 Power-up When the monostable multivibrator is powered-up, it may produce an output pulse with a pulse width defined by the values of R using the RC circuit on pin nRD shown in 12.2.2 Power-down A large capacitor (C to the energy stored in this capacitor ...

Page 16

... NXP Semiconductors 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

Page 17

... NXP Semiconductors SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 18

... NXP Semiconductors SSOP16: plastic shrink small outline package; 16 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT338-1 Fig 17. Package outline SOT338-1 (SSOP16) ...

Page 19

... NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 20

... NXP Semiconductors DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 21

... NXP Semiconductors 14. Revision history Table 10. Revision history Document ID Release date 74LV123_5 20071108 • Modifications: Changed: SOT38-1 changed into SOT38-4 74LV123_4 20070919 74LV123_3 20030313 74LV123_2 19980420 74LV123_1 19970204 74LV123_5 Product data sheet Dual retriggerable monostable multivibrator with reset Data sheet status ...

Page 22

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 23

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . . 6 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . 10 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12 Application information 12.1 Timing components . . . . . . . . . . . . . . . . . . . . 13 12 ...

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