74ACT280MTR STMicroelectronics, 74ACT280MTR Datasheet

IC PARITY GENERATR/CHECKR 14SOIC

74ACT280MTR

Manufacturer Part Number
74ACT280MTR
Description
IC PARITY GENERATR/CHECKR 14SOIC
Manufacturer
STMicroelectronics
Series
74ACTr
Datasheet

Specifications of 74ACT280MTR

Logic Type
Parity Generator/Checker
Number Of Circuits
9-Bit
Current - Output High, Low
24mA, 24mA
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-55°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
14-SOIC (0.154", 3.90mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
DESCRIPTION
The 74ACT280 is an advanced high-speed CMOS
9
fabricated with sub-micron silicon gate and
double-layer metal wiring C
It is composed of nine data inputs (A to I) and odd/
even parity outputs ( ODD and EVEN). The nine
data inputs control the output conditions. When
the number of high level input is odd,
output is kept high and EVEN output low.
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 2001
HIGH SPEED: t
LOW POWER DISSIPATION:
I
COMPATIBLE WITH TTL OUTPUTS
V
50 TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
BALANCED PROPAGATION DELAYS:
t
OPERATING VOLTAGE RANGE:
V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 280
IMPROVED LATCH-UP IMMUNITY
CC
PLH
BIT
OH
IH
CC
= 4 A(MAX.) at T
= 2V (MIN.), V
| = I
(OPR) = 4.5V to 5.5V
t
PHL
PARITY
OL
= 24mA (MIN)
PD
GENERATOR
IL
= 7ns (TYP.) at V
= 0.8V (MAX.)
A
=25°C
2
MOS tecnology.
9 BIT PARITY GENERATOR/CHECKER
CHECKER
CC
= 5V
ODD
ORDER CODES
Conservely, when the output is even,
output is kept high and ODD low.
The IC generates either odd or even parity making
it flexible application. The word-length capability is
easly expanded by cascading.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PACKAGE
TSSOP
SOP
DIP
DIP
74ACT280M
74ACT280B
TUBE
SOP
74ACT280
74ACT280MTR
74ACT280TTR
TSSOP
T & R
EVEN
1/9

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74ACT280MTR Summary of contents

Page 1

... Speed CMOS systems with TTL, NMOS and CMOS output voltage levels. All inputs and outputs are equipped with protection circuits against static discharge, giving ODD them 2KV ESD immunity and transient excess voltage. 74ACT280 SOP TSSOP TUBE T & R 74ACT280B 74ACT280M 74ACT280MTR 74ACT280TTR EVEN 1/9 ...

Page 2

INPUT AND OUTPUT EQUIVALENT CIRCUIT TRUTH TABLE NUMBER OF INPUTS THAT ARE HIGH LOGIC DIAGRAM 2/9 PIN DESCRIPTION PIN 10, 11, 12, 13 ...

Page 3

ABSOLUTE MAXIMUM RATINGS Symbol V Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Current ...

Page 4

DC SPECIFICATIONS Symbol Parameter V (V) V High Level Input 4.5 IH Voltage 5.5 V Low Level Input 4.5 IL Voltage 5.5 V High Level Output 4.5 OH Voltage 5.5 4.5 5.5 V Low Level Output 4.5 OL Voltage ...

Page 5

TEST CIRCUIT C = 50pF or equivalent (includes jig and probe capacitance 500 or equivalent pulse generator (typically OUT WAVEFORM: PROPAGATION DELAYS (f=1MHz; 50% duty cycle) ...

Page 6

Plastic DIP-14 MECHANICAL DATA DIM. MIN. a1 0. 1.27 6/9 mm TYP. MAX. MIN. 0.020 1.65 0.055 0.5 0.25 20 8.5 2.54 15.24 7.1 5.1 3.3 2.54 ...

Page 7

SO-14 MECHANICAL DATA mm DIM. MIN. TYP 0 0.35 b1 0. 8.55 E 5.8 e 1.27 e3 7.62 F 3.8 G 4 inch MAX. MIN. TYP. 1.75 0.2 ...

Page 8

DIM. MIN 0.05 A2 0.85 b 0.19 c 0.09 D 4.9 E 6. PIN 1 IDENTIFICATION 1 8/9 TSSOP14 MECHANICAL DATA mm TYP. MAX. 1.1 ...

Page 9

... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied ...

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