74HC597D,653 NXP Semiconductors, 74HC597D,653 Datasheet - Page 2

• Manufacturer Part Number: 74HC597D,653
• Description: IC SHIFT REGISTER 8BIT 16SOIC TR
• Manufacturer: NXP Semiconductors
• Series: 74HCr
• Type: Not Requiredr

Specifications of 74HC597D,653

• Package / Case: 16-SOIC (3.9mm Width)
• Logic Type: Shift Register
• Function: Parallel to Serial
• Output Type: Standard
• Number Of Elements: 1
• Number Of Bits Per Element: 8
• Voltage - Supply: 2 V ~ 6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Counting Sequence: Serial/Parallel to Serial
• Number Of Circuits: 1
• Logic Family: HC
• Propagation Delay Time: 16 ns
• Supply Voltage (max): 6 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 2 V
• Technology: CMOS
• Number Of Elements: 1
• Number Of Bits: 8
• Logical Function: Shift Register
• Operating Supply Voltage (typ): 5V
• Package Type: SOIC W
• Operating Temp Range: -40C to 125C
• Operating Supply Voltage (min): 2V
• Operating Supply Voltage (max): 6V
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 74HC597D-T; 74HC597D-T; 933757330653; Q2372891

Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. For HC the condition is V
ORDERING INFORMATION
See
December 1990
t
f
C
C
PHL
max
SYMBOL
8-bit parallel storage register inputs
Shift register has direct overriding load and clear
Output capability: standard
I
8-bit shift register with input flip-flops
I
PD
CC
f
f
C
V
For HCT the condition is V
i
o
“74HC/HCT/HCU/HCMOS Logic Package Information”
/ t
CC
PD
L
category: MSI
= output frequency in MHz
= input frequency in MHz
(C
PLH
= output load capacitance in pF
P
is used to determine the dynamic power dissipation (P
= supply voltage in V
L
D
= C
V
amb
CC
propagation delay
maximum clock frequency SH
input capacitance
power dissipation capacitance per package
PD
2
SH
ST
PL to Q
= 25 C; t
V
CP
CP
f
o
CC
) = sum of outputs
to Q
to Q
2
f
r
i
= t
+
PARAMETER
I
I
f
= GND to V
= GND to V
= 6 ns
(C
L
V
CC
2
CC
CC
CP
f
o
) where:
1.5 V
2
.
C
notes 1 and 2
GENERAL DESCRIPTION
The 74HC/HCT597 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT597 consist each of an 8-bit storage
register feeding a parallel-in, serial-out 8-bit shift register.
Both the storage register and the shift register have
positive edge-triggered clocks. The shift register also has
direct load (from storage) and clear inputs.
L
D
= 15 pF; V
in W):
CONDITIONS
CC
= 5 V
17
25
21
96
3.5
29
HC
TYPICAL
74HC/HCT597
Product specification
20
29
26
83
3.5
32
HCT
ns
ns
ns
MHz
pF
pF
UNIT