N74F299D,602 NXP Semiconductors, N74F299D,602 Datasheet - Page 2

• Manufacturer Part Number: N74F299D,602
• Description: IC SHIFT REGISTER 8BIT 20SOIC
• Manufacturer: NXP Semiconductors
• Series: 74Fr

Specifications of N74F299D,602

• Logic Type: Shift Register
• Output Type: Standard
• Number Of Elements: 1
• Number Of Bits Per Element: 8
• Function: Universal
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 933828960602; N74F299D; N74F299D

FEATURES
DESCRIPTION
The 74F299 is an 8-bit universal shift/storage register with 3-State
outputs. Four modes of operation are possible: Hold (store), shift
left, shift right and parallel load. The parallel load inputs and flip-flop
outputs are multiplexed to reduce the total number of package pins.
Additional outputs are provided for flip-flops Q0 and Q7 to allow
easy serial cascading. A separate active-LOW Master Reset is used
to reset the register.
The 74F299 contains eight edge-triggered D-type flip-flops and the
interstage logic necessary to perform synchronous shift left, shift
right, parallel load and hold operations. The type of operation is
determined by S0 and S1, as shown in the Function Table. All
flip-flop outputs are brought out through 3-State buffers to separate
I/O pins that also serve as data inputs in the parallel load mode.
Q0 and Q7 are also brought out on other pins for expansion in serial
shifting of longer words.
A LOW signal on MR overrides the Select and CP inputs and resets
the flip-flops. All other state changes are initiated by the rising edge
of the clock. Inputs can change when the clock is in either state
provided only that the recommended set-up and hold times, relative
to the rising edge of clock are observed.
A HIGH signal on either OE0 or OE1 disables the 3-State buffers
and puts the I/O pins in the high impedance state. In this condition
the shift, hold, load and reset operations can still occur. The 3-State
buffers are also disabled by High signals on both S0 and S1 in
preparation for a parallel load operation.
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20 A in the HIGH State and 0.6 mA in the LOW state.
Philips Semiconductors
2003 Feb 05
DS0
DS7
S0, S1
CP
MR
OE0, OE1
Q0, Q7
I/On
I/On
Common parallel I/O for reduced pin count
Additional serial inputs and outputs for expansion
Four operating modes: Shift left, shift right, load and store
3-State outputs for bus-oriented applications
8-bit universal shift/storage register (3-State)
PINS
Serial data input for right shift
Serial data input for left shift
Mode select inputs
Clock pulse input (Active rising edge)
Asynchronous Master Reset input (Active LOW)
Output Enable input (Active LOW)
Serial outputs
Multiplexed parallel data inputs
3-State parallel outputs
DESCRIPTION
2
PIN CONFIGURATION
ORDERING INFORMATION
74F299
20-pin plastic SOL
20-pin plastic DIP
TYPE
DESCRIPTION
GND
TYPICAL f
OE0
OE1
I/O6
I/O4
I/O2
I/O0
MR
Q0
S0
115 MHz
10
1
2
3
4
5
6
7
8
9
T
amb
V
COMMERCIAL
ORDER CODE
CC
MAX
HIGH / LOW
= 0 C to +70 C
N74F299N
N74F299D
74F(U.L.)
RANGE
= 5 V 10%,
1.0 / 1.0
1.0 / 1.0
1.0 / 2.0
1.0 / 1.0
1.0 / 1.0
1.0 / 1.0
3.5 / 1.0
150 / 40
50 / 33
SF00865
20
19
18
17
16
15
14
13
12
11
SUPPLY CURRENT
V
S1
DS7
Q7
I/O7
I/O5
I/O3
I/O1
CP
DS0
CC
TYPICAL
(TOTAL)
1.0 mA / 20 mA
3.0 mA / 24 mA
20 A / 0.6 mA
20 A / 0.6 mA
20 A / 1.2 mA
20 A / 0.6 mA
20 A / 0.6 mA
20 A / 0.6 mA
70 A / 0.6 mA
LOAD VALUE
58 mA
74F299
HIGH / LOW
PKG DWG #
SOT146-1
SOT163-1
Product data