MB81V18165B-60LPFTN Fujitsu, MB81V18165B-60LPFTN Datasheet

MB81V18165B-60LPFTN

Manufacturer Part Number

MB81V18165B-60LPFTN

Description

DRAM 1Mx16-60, EDO, 3.3V, TSOP, 1k, Self- Ref, Low-Power

Manufacturer

Fujitsu

Datasheet

1.MB81V18165B-60LPFTN.pdf (31 pages)

Specifications of MB81V18165B-60LPFTN

Package

Tray/JP

Unit

1170

Date_code

00+

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FUJITSU SEMICONDUCTOR

MEMORY

CMOS

1 M

HYPER PAGE MODE DYNAMIC RAM

MB81V18165B-50/-60/-50L/-60L

RAS Access Time

Random Cycle Time

Address Access Time

CAS Access Time

Hyper Page Mode Cycle Time

Low Power

Dissipation

DESCRIPTION

PRODUCT LINE & FEATURES

The Fujitsu MB81V18165B is a fully decoded CMOS Dynamic RAM (DRAM) that contains 16,777,216 memory

cells accessible in 16-bit increments. The MB81V18165B features a “hyper page” mode of operation whereby

high-speed random access of up to 1,024

MB81V18165B DRAM is ideally suited for mainframe, buffers, hand-held computers video imaging equipment,

and other memory applications where very low power dissipation and high bandwidth are basic requirements of

the design. Since the standby current of the MB81V18165B is very small, the device can be used as a non-

volatile memory in equipment that uses batteries for primary and/or auxiliary power.

The MB81V18165B is fabricated using silicon gate CMOS and Fujitsu’s advanced four-layer polysilicon and two-

layer aluminum process. This process, coupled with advanced stacked capacitor memory cells, reduces the

possibility of soft errors and extends the time interval between memory refreshes. Clock timing requirements for

the MB81V18165B are not critical and all inputs are LVTTL compatible.

DATA SHEET

• 1,048,576 words

• Silicon gate, CMOS, Advanced Stacked

• All input and output are LVTTL compatible

• 1,024 refresh cycles every 16.4 ms

• Self refresh function (Low power version)

• Early write or OE controlled write capability

Capacitor Cell

Parameter

Operating Current

Standby

Current

16 BIT

CMOS 1,048,576 16 Bit Hyper Page Mode Dynamic RAM

LVTTL level

CMOS level

16 bits organization

3.6 mW max.

1.8 mW max.

-50

16 bits of data within the same row can be selected. The

648 mW max.

25 ns max.

50 ns max.

13 ns max.

20 ns min.

84 ns min.

• RAS-only, CAS-before-RAS, or Hidden Refresh

• Hyper Page Mode, Read-Modify-Write

• On chip substrate bias generator for high

• Standard and low power versions

capability

performance

0.54 mW max.

3.6 mW max.

-50L

MB81V18165B

3.6 mW max.

1.8 mW max.

-60

540 mW max.

104 ns min.

60 ns max.

30 ns max.

15 ns max.

25 ns min.

DS05-11304-4E

0.54 mW max.

3.6 mW max.

-60L

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