MT48LC2M32B2P-7 IT Micron Semiconductor Products, MT48LC2M32B2P-7 IT Datasheet
![no-image](/images/no-image-200.jpg)
MT48LC2M32B2P-7 IT
Manufacturer Part Number
MT48LC2M32B2P-7 IT
Description
Manufacturer
Micron Semiconductor Products
Datasheet
1.MT48LC2M32B2TG-7-IT.pdf
(69 pages)
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Synchronous DRAM
MT48LC2M32B2 – 512K x 32 x 4 banks
For the latest data sheet, refer to Micron’s Web site
Features
• PC100 functionality
• Fully synchronous; all signals registered on positive
• Internal pipelined operation; column address can be
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto precharge,
• Self refresh mode
• 64ms, 4,096-cycle refresh (15.6µs/row)
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
• Supports CAS latency (CL) of 1, 2, and 3
Notes: 1. Off-center parting line.
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_1.fm - Rev. I 10/07 EN
Options
• Configuration
• Plastic package – OCPL
• Timing (cycle time)
• Die revision
• Operating temperature range
edge of system clock
changed every clock cycle
and auto refresh modes
– 2 Meg x 32 (512K x 32 x 4 banks)
– 86-pin TSOP II (400 mil)
– 86-pin TSOP II (400 mil) Pb-free
– 90-ball VFBGA (8mm x 13mm) lead-
– 5ns (200 MHz)
– 5.5ns (183 MHz)
– 6ns (166 MHz)
– 7ns (143 MHz)
– Commercial (0° to +70°C)
– Extended (–40°C to +85°C)
free
2. Available on -6 and -7.
MT48LC2M32B2P-7:G
Products and specifications discussed herein are subject to change by Micron without notice.
Part Number Example:
1
Marking
2M32B2
None
-55
IT
TG
B5
:G
-5
-6
-7
P
2
1
Table 1:
Table 2:
Table 3:
Notes: 1. FBGA Device Decode: http://
Configuration
Refresh count
Row addressing
Bank addressing
Column addressing
MT48LC2M32B2TG
MT48LC2M32B2P
MT48LC2M32B2B5
Speed
Grade
-55
-5
-6
-7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Part Number
www.micron.com/support/FBGA/FBGA.asp
Frequency
200 MHz
183 MHz
166 MHz
143 MHz
Address Table
Key Timing Parameters
CL = CAS (READ) latency
64Mb (x32) SDRAM Part Number
Clock
1
Access
CL = 3
Time
4.5ns
5.5ns
5.5ns
5ns
©2001 Micron Technology, Inc. All rights reserved.
64Mb: x32 SDRAM
512K x 32 x 4 banks
Architecture
4 (BA0, BA1)
2K (A0–A10)
2 Meg x 32
256 (A0–A7)
Setup
2 Meg x 32
2 Meg x 32
2 Meg x 32
Time
1.5ns
1.5ns
1.5ns
2ns
4K
Features
Hold
Time
1ns
1ns
1ns
1ns
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