74ACT323PC Fairchild Semiconductor, 74ACT323PC Datasheet - Page 2

• Manufacturer Part Number: 74ACT323PC
• Description: IC SHIFT/REGISTER STORE 20DIP
• Manufacturer: Fairchild Semiconductor
• Series: 74ACTr

Specifications of 74ACT323PC

• Logic Type: Register, Bidirectional
• Output Type: Standard
• Number Of Elements: 1
• Number Of Bits Per Element: 8
• Function: Universal
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 20-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Functional Description
The ACT323 contains eight edge-triggered D-type flip-flops
and the interstage logic necessary to perform synchronous
reset, shift left, shift right, parallel load and hold operations.
The type of operation is determined by S
in the Mode Select Table. All flip-flop outputs are brought
out through 3-STATE buffers to separate I/O pins that also
serve as data inputs in the parallel load mode. Q
are also brought out on other pins for expansion in serial
shifting of longer words.
A LOW signal on SR overrides the Select inputs and allows
the flip-flops to be reset by the next rising edge of CP. All
Mode Select Table
H
L

X
LOW Voltage Level
HIGH Voltage Level
Immaterial
LOW-to-HIGH Clock Transition
SR
H
H
H
L
H
S
X
H
H
L
L
1
Inputs
0
and S
S
X
H
H
L
L
0
1
as shown
0
and Q
CP




X
7
Synchronous Reset; Q
Parallel Load; I/O
Shift Left; DS
Hold
Shift Right; DS
2
other state changes are also initiated by the LOW-to-HIGH
CP transition. Inputs can change when the clock is in either
state provided only that the recommended setup and hold
times, relative to the rising edge of CP, are observed.
A HIGH signal on either OE
buffers and puts the I/O pins in the high impedance state.
In this condition the shift, load, hold and reset operations
can still occur. The 3-STATE buffers are also disabled by
HIGH signals on both S
lel load operation.
7
Response
0
Q
n
7
Q
, Q
0
Q
, Q
n
7
0
–Q
0
Q
7
6
Q
, etc.
0
1
LOW
, etc.
and S
1
or OE
1
in preparation for a paral-
2
disables the 3-STATE