MSM7731-02 OKI [OKI electronic componets], MSM7731-02 Datasheet - Page 10

• Manufacturer Part Number: MSM7731-02
• Description: Dual Echo Canceler & Noise Canceler with Dual Codec for Hands-Free
• Manufacturer: OKI [OKI electronic componets]

LGC
LGC
LGC
LGC/AGC
This pin turns ON or OFF the gain control function to control the input level and prevent howling by means of gain
controls (GainL/A) provided in the RinL/A inputs of the echo canceler. The gain controller adjusts the RinL/A
input level when it is –10 dBm0 or above, and it has the control range of 0 to –8.5 dB. A logic “0” turns the
function ON and a logic “1” turns the function OFF. This function is valid when the LTHR/ATHR pin is in the
mormal mode. Because data is shifted into this pin in synchronization with the rising edge of the SYNC signal,
hold the data at the pin for 250 s or longer. This pin is ORed with the CR4-B0 and CR5-B0 bits of the control
register. Refer to the section “RELATIONSHIP BETWEEN PINS AND CONTROL REGISTERS”.
Notes:
Lxx/Axx : In the above, Lxx refers to line echo canceler control pins and Axx to acoustic echo canceler control
xxL/xxA : In the above pin descriptions, xxL refers to line echo canceler functions and xxA to acoustic echo
GLPADTHR
GLPADTHR
GLPADTHR
GLPADTHR
This is the mode control pin for the attenuators (LPADL/A) provided in the SinL/A inputs and the amplifiers
(GPADL/A) provided in the SoutL/A outputs of the echo canceler. A logic “0” selects the “through mode” and a
logic “1” selects the normal mode (PAD operation). The levels are set by the CR10 register. Settings of ± 18, ± 12,
± 6 and 0 dB are possible. The default setting is ± 12 dB. If the echo return loss (value of returned echo) is
amplified, set the LPAD level such that echo return loss will be attenuated. It is recommended to set the GPAD
level to the positive level equal to the LPAD level. If the pin setting is changed, the coefficient reset must be
activated by either the RST pin or the RST bit (CR0-B6). Because data is shifted into this pin in synchronization
with the rising edge of the SYNC signal, hold the data at the pin for 250 s or longer. This pin is ORed with the
CR1-B2 bit of the control register. Refer to the section “RELATIONSHIP BETWEEN PINS AND CONTROL
REGISTERS”.
RST
RST
RST
RST
This input pin resets coefficients of the echo canceler and noise canceler. A logic “0” causes the reset state to be
entered. At this time, the filter coefficients for the echo canceler and noise canceler are reset. Control register
contents are preserved. While reset is being processed, there is not sound. During normal operation, set this pin to
a logic “1”. Use this pin in cases where the echo path changes (due to line switching during a telephone
conversation, etc.), or when resuming telephone communication. Because data is shifted into this pin in
synchronization with the rising edge of the SYNC signal, hold the data at the pin for 250 s or longer. This pin is
ORed (negative logic) with the CR0-B6 bit of the control register. Refer to the section “RELATIONSHIP
BETWEEN PINS AND CONTROL REGISTERS”.
1 Semiconductor
AGC
AGC
AGC
pins.
canceler functions.
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