MSM7731-02 OKI [OKI electronic componets], MSM7731-02 Datasheet - Page 7

• Manufacturer Part Number: MSM7731-02
• Description: Dual Echo Canceler & Noise Canceler with Dual Codec for Hands-Free
• Manufacturer: OKI [OKI electronic componets]

FEDL7731-02-04
1 Semiconductor
MSM7731-02
PCMEI
This is the massage signal input pin. Use this pin when a massage is output to the speaker on the acoustic-side. This
input signal is shifted at the rising edge of the BCLK signal and then input. The beginning of digital data is
identified on the rising edge of the SYNC signal. The coding format can be selected as -law PCM or 16-bit linear
(2’s complement) by the PCMSEL pin or PCMSEL (CR11-B1) bit. If the PCMEI pin is not used, set it to a logic
“1” if -law PCM has been selected, or a logic “0” if 16-bit linear mode has been selected. The sync format can be
selected as normal-sync or short-frame sync by the SYNCSEL pin. Timing is the same as for the PCMI pin (refer
to Figure 3). This digital input signal is added internally to the echo canceler output signal. Be careful of overflow
during telephone conversations.
PCMEO
This output pin is for memo recording. Use it with the memo function. This output signal is synchronized to the
rising edge of the BCLK an SYNC signals and then output. When not used for output, this pin is in the high
impedance state. It is also at high impedance during the power-down reset and the initial modes. The coding format
can be selected as -law PCM or 16-bit linear (2’s complement) by the PCMSEL pin or PCMSEL (CR11-B1) bit.
The sync format can be selected as normal-sync or short-frame-sync by the SYNCSEL pin. Timing is the same as
for the PCMO pin (refer to Figure 3).
SYNCSEL
This is the sync timing selection pin for digital data communication. A logic “0” selects normal-sync timing and a
logic “1” selects short-frame-sync timing. Refer Figure 3 for the timing. If the pin setting is changed, reset must be
activated by either the PDN/RST pin or the PDN/RST bit (CR0-B7)
PCMSEL
This is the coding format selection pin for digital data communication. A logic “1” selects -law PCM and a logic
“0” selects 16-bit linear (2’s complement) coding format. When an internal clock is selected, the BCLK signal
determines the output clock frequency. If the digital interface is not used, set this pin to logic “0” to select 16-bit
linear coding format.
If the pin setting is changed, reset must be performed by either the PDN/RST pin or the PDN/RST bit (CR0-B7).
This pin is logically ORed with the PCMSEL bit (CR11-B1). Refer to the section “RELATIONSHIP BETWEEN
PINS AND CONTROL REGISTERS”.
SLPTHR
This is the “through mode” control pin for the transmit slope filter. In the “through mode”, the filter is halted and
data is directly output. A logic “0” selects the normal mode (slope filter operation) and a logic “1” selects the
“through mode”. The slope filter decreases noises of low frequencies and improves speech quality. Refer to the
slope filter frequency characteristics. Because data is shifted into this pin in synchronization with the rising edge of
the SYNC signal, hold the data at the pin for 250 s or longer. For further details, refer to the electrical
characteristics. This pin is ORed with the CR1-B1 bit of the control register. Refer to the section
“RELATIONSHIP BETWEEN PINS AND CONTROL REGISTERS”.
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