MSM7731-02 OKI [OKI electronic componets], MSM7731-02 Datasheet - Page 38

• Manufacturer Part Number: MSM7731-02
• Description: Dual Echo Canceler & Noise Canceler with Dual Codec for Hands-Free
• Manufacturer: OKI [OKI electronic componets]

B7
B6 to B2 Reserved bits.
B1
B0
1 Semiconductor
Initial Value
SYPDN (CR11-B0)
Internal process
Power-down removal method
After removing power-down
Operating Current
(12) CR11 (SYNC power-down control register)
CR11
Data write flag
After power-down reset is released, this device enters the initial mode.
This bit becomes “1” only during the initial mode, enabling access to the internal data memory.
Checking this bit will detect whether writing by an external microcomputer is possible.
PCM coding format control
This is the coding format selection bit for digital data communication. A logic “1” selects µ-law PCM
and a logic “0” selects 16-bit linear (2’s complement) coding format. The BCLK signal determines the
output clock frequency to be used when internal clock is selected.
If the digital interface is not used, set this bit to logic “0” to select 16-bit linear coding format. Since this
bit is ORed with the PCMSEL pin, set this bit to logic “0” when controlling by the pin. If this bit setting
is changed, reset must be activated by either the PDN/RST pin or the PDN/RST bit (CR0-B7).
SYNC-PDWN control
This bit controls the function that automatically enters the power-down state when the SYNC signal is
fixed to a logic “1” or “0”. This function is valid when the external clock mode has been selected by the
CLKSEL pin. Two kinds of power-down modes can be selected.
• PDN/RST power-down mode
If the SYNC signal is fixed at 8 kHz or longer, this device automatically writes a logic 1 to the control
register PDN/RST bit (CR0-B7) and enters the power-down reset state. To return to the normal
operation, reset must be activated by either the PDN/RST pin or the PDN/RST bit (CR0-7).
The state after returning to the normal operation is the same as that reset after power-on.
• PDWN power-down mode
If the SYNC signal is fixed at 8 kHz or longer, this device automatically enters the power-down state.
During the power-down, the analog output is “0” output (mute) and the SG output holds about 1.4 V. To
return to the normal operation, detect the SYNC signal rise. In the state after returning to the normal
operation, internal variables and coefficients of the echo canceler and noise canceler are reset. Each bit
of the control register is held and operates normally after about 200 ms.
READY
B7
0
B6
—
0
PDN/RST (CR0-B7) = 1
PDN/RST pin or bit
–Reset
Each bit of CR.
Internal coefficient.
Echo canceler coefficient.
Noise canceler coefficient.
Typ. 0.02 mA
1: write enabled
Modification of initial values is inhibited.
1: µ-law PCM
1: PDN/RST power-down
B5
—
0
PDN/RST power-down
1
B4
—
0
0: write disabled
0: 16-bit linear
B3
—
0
0: PDWN power-down
Mute control
SYNC rising edge
–Reset
Internal coefficient.
Echo canceler coefficient.
Noise canceler coefficient.
–Hold
Each bit of CR.
TBD
B2
—
0
PDWN power-down
PCMSEL
0
B1
0
FEDL7731-02-04
MSM7731-02
SYPDN
B0
0
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