MT91L60AS MITEL [Mitel Networks Corporation], MT91L60AS Datasheet - Page 11

• Manufacturer Part Number: MT91L60AS
• Description: ISO2-CMOS 3 Volt Multi-Featured Codec (MFC)
• Manufacturer: MITEL [Mitel Networks Corporation]

the resynchronization circuitry activity and will not
affect operation since the bit cell period at 128 kb/s
and 256 kb/s is relatively large. There is a one frame
delay through the FDI circuit for asynchronous
operation. Refer to the specifications of Figures 12
& 13 for both synchronous and asynchronous SSI
timing.
PWRST/Software Reset (Rst)
While the MT91L60 is held in PWRST no device
control or functionality is possible. While in software
reset (Rst=1, address 03h) only the microport is
functional. Software reset can only be removed by
writing Rst logic low or by setting the PWRST pin.
Advance Information
00
01
02
03
04
05
06
07
PDFDI
RxINC
CEN
C
D
-
-
-
7
7
RxFG
PDDR
DEN
C
D
-
-
-
6
6
2
3V Multi-featured Codec Register Map
RxFG
RST
D8
C
D
-
-
-
5
5
1
RxFG
A/
C
D
-
-
-
-
4
4
0
ANALOG
T
TxINC
Smag/
ITU-T
PCM/
x
Mute
C
D
After Power-up reset (PWRST) or software reset
(Rst) all control bits assume their default states;
gains as well as the device powered up in SSI mode
2048 kb/s operation with Dout tri-stated while there
is no strobe active on STB.
supplied to STB, then Dout will be active, during the
defined channel.
To attain complete power-down from a normal
operating condition, write PDFDI = 1 and PDDR = 1
(Control Register 1, address 03h) or put PWRST pin
low.
-
-
3
3
-Law functionality, usually 0 dB programmable
R
loopen
TxFG
STG
CSL
x
Mute
C
D
-
2
2
2
2
2
T
TxFG
STG
CSL
x
C
D
Bsel
-
-
1
1
1
1
1
DrGain
R
TxFG
STG
CSL
x
C
D
Bsel
-
0
0
If a valid strobe is
0
0
0
MT91L60
Gain Control
Gain Control
Path Control
C-Channel
D-Channel
Loop Back
Register 1
Register 2
Register 1
Register 2
Register
Register
Control
Control
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