MT91L60AS MITEL [Mitel Networks Corporation], MT91L60AS Datasheet - Page 2

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MT91L60AS

Manufacturer Part Number
MT91L60AS
Description
ISO2-CMOS 3 Volt Multi-Featured Codec (MFC)
Manufacturer
MITEL [Mitel Networks Corporation]
Datasheet

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Part Number:
MT91L60AS
Manufacturer:
MITEL
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MT91L60
7-108
Pin Description
SOIC
10
1
2
3
4
5
6
7
8
9
Pin #
DIP
10
12
11
1
2
4
5
6
7
8
PWRST Power-up Reset (Input). CMOS compatible input with Schmitt Trigger (active low).
A/ /IRQ
20 PIN SOIC
DATA 1
DATA 2
24 PIN PDIP
Name
SCLK
V
V
V
CS
IC
SSD
Bias
Ref
Bias Voltage (Output). (V
amplifiers. Connect 0.1 µF capacitor to V
Reference Voltage for Codec (Output). Used internally. Connect 0.1 µF capacitor
to V
Internal Connection. Tie externally to V
A/ - When internal control bit DEn = 0 this CMOS level compatible input pin governs
the companding law used by the filter/Codec; -Law when tied to V
when tied to V
IRQ - When internal control bit DEn = 1 this pin becomes an open-drain interrupt
output signalling valid access to the D-Channel registers in ST-BUS mode.
Digital Ground. Nominally 0 volts.
Chip Select (Input). This input signal is used to select the device for microport data
transfers. Active low. CMOS level compatible.
Serial Port Synchronous Clock (Input). Data clock for microport. CMOS level
compatible.
Bidirectional Serial Data. Port for microprocessor serial data transfer. In Motorola/
National mode of operation, this pin becomes the data transmit pin only and data
receive is performed on the DATA 2 pin. Input CMOS level compatible.
Serial Data Receive. In Motorola/National mode of operation, this pin is used for
data receive. In Intel mode, serial data transmit and receive are performed on the
DATA 1 pin and DATA 2 is disconnected. Input CMOS level compatible.
SSA
.
PWRST
A/ /IRQ
PWRST
A/ /IRQ
DATA1
DATA2
DATA1
DATA2
VSSD
VBias
SCLK
VSSD
VBias
SCLK
VRef
VRef
DD
CS
NC
NC
CS
IC
IC
Figure 2 - Pin Connections
. Logically OR’ed with A/ register bit.
10
11
12
10
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
DD
/2) volts is available at this pin for biasing external
24
23
22
21
20
19
18
17
16
15
14
13
20
19
18
17
16
15
14
13
12
11
Description
M +
M -
VSSA
VDD
CLOCKin
STB/F0i
Din
Dout
HSPKR +
HSPKR -
M +
M -
VSSA
NC
HSPKR +
HSPKR -
VDD
CLOCKin
NC
STB/F0i
Din
Dout
SS
SSA
for normal operation.
.
Advance Information
SS
and A-Law

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