MT91L60AS MITEL [Mitel Networks Corporation], MT91L60AS Datasheet - Page 7

• Manufacturer Part Number: MT91L60AS
• Description: ISO2-CMOS 3 Volt Multi-Featured Codec (MFC)
• Manufacturer: MITEL [Mitel Networks Corporation]

Advance Information
The data streams operate at 2048 kb/s and are Time
Division Multiplexed into 32 identical channels of 64
kb/s bandwidth. A frame pulse (a 244 nSec low going
pulse) is used to parse the continuous serial data
streams into the 32 channel TDM frames. Each
frame has a 125 µSecond period translating into an 8
kHz frame rate. A valid frame begins when F0i is
DATA 1
RECEIVE
DATA 1
TRANSMIT
SCLK
CS
DATA 2
RECEIVE
DATA 1
TRANSMIT
SCLK
CS
subsequent byte is always data until terminated via CS returning high.
subsequent byte is always data until terminated via CS returning high.
The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The
The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The
Delays due to internal processor timing which are transparent .
A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.
The COMMAND/ADDRESS byte contains:
Delays due to internal processor timing which are transparent.
The MT91L60:-latches received data on the rising edge of SCLK.
A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.
The COMMAND/ADDRESS byte contains:
The MT91L60:-latches received data on the rising edge of SCLK.
D
D
7
0
D
D
Figure 6 - Serial Port Relative Timing for Motorola Mode 00/National Microwire
-outputs transmit data on the falling edge of SCLK.
-outputs transmit data on the falling edge of SCLK.
COMMAND/ADDRESS
6
COMMAND/ADDRESS
1
D
D
5
2
D
D
4
3
D
D
3
4
Figure 5 - Serial Port Relative Timing for Intel Mode 0
D
D
2
5
D
D
1
6
D
D
0
7
1 bit - Read/Write
3 bits - Addressing Data
4 bits - Unused
1 bit - Read/Write
3 bits - Addressing Data
4 bits - Unused
D
D
D
D
7
0
0
7
D
D
D
D
6
1
1
6
DATA INPUT/OUTPUT
DATA INPUT/OUTPUT
D
D
D
D
5
2
2
5
D
D
D
D
4
3
3
4
D
D
D
logic low coincident with a falling edge of C4i. Refer
to Figure 11 for detailed ST-BUS timing. C4i has a
frequency (4096 kHz) which is twice the data rate.
This clock is used to sample the data at the 3/4
bit-cell position on DSTi and to make data available
on DSTo at the start of the bit-cell. C4i is also used to
clock the MT91L60 internal functions (i.e., Filter/
D
3
4
4
3
D
D
D
D
2
5
5
2
D
D
D
D
1
6
6
1
D
R/W
X
7
D
D
D
D
D
7
0
7
0
7
X
X
D
D
D
D
0
7
0
7
X
X
D
D
D
D
1
6
1
6
COMMAND/ADDRESS:
COMMAND/ADDRESS:
D
D
D
D
X
X
2
5
2
5
D
D
D
D
3
4
3
A
4
A
2
D
D
2
D
D
4
3
4
3
D
A
D
MT91L60
D
D
A
1
2
5
5
2
1
D
D
D
D
1
6
6
1
A
A
0
D
D
D
D
0
0
7
7
0
R/W
D
D
X
0
0
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