ZL30226/GA ZARLINK [Zarlink Semiconductor Inc], ZL30226/GA Datasheet - Page 29

• Manufacturer Part Number: ZL30226/GA
• Description: 4/8/16 Port IMA/TC PHY Device for xDSL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

ZL30228 Pin Description (continued)
B17,C17,A18,
B18,D18,C18,
AC16,AE16,
AF16,AC15,
AE15,AF15,
AD14,AE14
A19,B19
Pin #
AF13
AF14
AC1
AD1
C19
D19
A4
D7
A5
B6
C6
B5
C7
B4
RXRingSync
RXRingData
TXRingData
RXRingClk
LatchClk
Name
Reset
TRST
Test1
Test2
Test3
Test4
TMS
TDO
[7:0]
[7:0]
TCK
TDI
Clk
I/O
O TDM Ring TX Data[7:0]. Data Bus connecting the TX TDM Ring port to the
O JTAG Test Data Output. Note: TDO is tristated by TRST pin.
O Test2. Must be left not connected (NC).
O Test4. Must be left not connected (NC)
I
I
I
I
I
I
I
I
I
I
I
I
RX TDM Ring port. Should be connected to the RXRingData inputs of the next
ZL30228 device in the Ring. These output are in High Z state if the TDM Ring
is not used.
TDM Ring RX Clock. Clock input signal used to align the RXRingSync and
RXRingData. Should be connected to the TXRingClk input of the previous
ZL30228 device in the Ring. There is an internal weak pull-down on this input.
TDM Ring RX Sync. Synchronization input signal used to retrieve data and
control from the bytes on RXRingData. Should be connected to the
TXRingSync output of the previous ZL30228 device in the Ring. There is an
internal weak pull-down on this input.
TDM Ring RX Data[7:0]. Data Bus connecting the RX TDM Ring port to the
TX TDM Ring port. Should be connected to the TXRingData inputs of the
previous ZL30228 device in the Ring. There are internal weak pull-downs on
these inputs.
System Clock (50 MHz nominal). In the ZL30228, this clock is used for all
internal operations of the device.
Counter Latch Clock. The clock present at this input can be divided internally
to produce the latch signal for the internal counters. Refer to the Counter
Transfer Command register for more details. This pin has an internal
pull-down.
System Reset. This is an active low input signal. It causes the device to enter
the initial state. The Clk signal must be active to reset the internal registers.
JTAG Test Clock. TCK should be pulled down if not used.
JTAG Test Mode Select. TMS is sampled on the rising edge of TCK.
JTAG Test Data Input. This pin has an internal weak pull-down.
JTAG Test Reset (active low). Should be asserted LOW on power-up and
during reset. Must be HIGH for JTAG boundary-scan operation. This pin has
an internal weak pull-down.
Test1. Must be tied Low.
Test3. Must be pulled up to V3.3 for normal operation. NOT 5 V TOLERANT.
Zarlink Semiconductor Inc.
ZL30226/7/8
System Signals
Power Signals
29
Description
Data Sheet