ZL30226/GA ZARLINK [Zarlink Semiconductor Inc], ZL30226/GA Datasheet - Page 91

• Manufacturer Part Number: ZL30226/GA
• Description: 4/8/16 Port IMA/TC PHY Device for xDSL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Bit #
15:6
Bit #
Bit #
13:8
15:3
5:2
7:0
15
14
1
0
2
1
0
Type
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
Unused. Always 0.
Reserved. Write 0.
0: Compare entire cell.
1: Compare entire ICP cell.
0: Global debugging disabled.
1: Global debugging enabled.
A 0 indicates that this word contains the last byte in the RX Cell processed FIFO for the
current link.
A 1 indicates that there is more bytes that were processed.
A 1 indicates that this word contains the last byte from the RX Cell that was processed.
A 0 indicates that there is more bytes that were processed from the same cell.
Cell Offset for the byte found to be different (number range between 1 and 53).
Byte content found to be different from the last received Cell.
Unused. Read all 0’s.
Ring Enable:
0: RING is NOT used and the output tri-state buffers are disabled (High Z mode).
1: RING is used and the output tri-state buffers are enabled (active).
Ring Initialization: Valid only for Ring Master
0: RUN mode.
1: INITIALIZATION mode. The MASTER device generates empty HEADER bytes to
initialize the RING.
Ring Master
0: This device is not the MASTER of the RING.
1: This device is the MASTER of the RING (Only 1 device can be MASTER on a RING)
0x0108
1 register for debug.
0000
0x0140 - 0x014F (16 reg)
1 register per RX Link pre-processed FIFO links.
8000
0x0180 (1 reg)
1 register for TDM Ring Tx.
0000
Table 51 - Processed RX Cell link FIFO Register
Table 50 - ICP Cell RAM DEBUG Register
Table 52 - Ring Tx Control Register
Zarlink Semiconductor Inc.
ZL30226/7/8
91
Description
Description
Description
Data Sheet