ZL30226/GA ZARLINK [Zarlink Semiconductor Inc], ZL30226/GA Datasheet - Page 43

• Manufacturer Part Number: ZL30226/GA
• Description: 4/8/16 Port IMA/TC PHY Device for xDSL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

When a valid HEC is found, the CD circuit locks on the cell boundary and enters the PRESYNC state. The
PRESYNC state keeps checking the HEC to ensure that the previous indication was not false. False indications are
interpreted to mean the circuit is not tracking valid ATM cells. After entering the PRESYNC state, the first false
indication triggers a transition back to HUNT state.
If the PRESYNC state HEC is correct, then a transition to the SYNC state occurs after “δ” cells (DELTA in ITU I.432)
are correctly received. In the SYNC state, the CD circuit treats the incoming ATM cell stream as stable and the
ZL30226/7/8 functions normally.
While in the SYNC state, if an incorrect HEC is obtained “α” consecutive times (ALPHA in ITU I.432), cell
delineation is considered lost and a transition is made back to the HUNT state (see Figure 7).
As defined by the ITU I.432 recommendations, the value of ALPHA and DELTA determine the robustness of the
delineation method. The value of ALPHA and DELTA for the Cell Delineation state machine are defined in the Cell
Delineation (0x00C9) register. Only one set of values is defined for the sixteen Cell Delineation state machines.
The status of the CD state machine for each link is available in bits 0 through 15 of the Cell Delineation Status
(0x00E6) register.
The ITU I.432 suggested values are: ALPHA = 7; and DELTA = 6.
Loss of Cell Delineation (LCD) is detected by counting the number of incorrect cells while in HUNT state. The
ZL30226/7/8 provides an internal Loss of Delineation (0x00C8) register to set the threshold for this count. The
LCD state for each link is available in bit 1 of the IRQ Link Status (0x0435 - 0x4444) registers, and in bit 6 of the
RX Link ID Number (0x00E3) register.
The LCD and End of LCD status bit reports the current condition of the Cell Delineation State Machine at the time it
is read, and can optionally generate an interrupt (IRQ). Table 3 provides the time, in microseconds, for the CD
circuit to receive a full ATM cell from the SHDSL emulating T1 payload and SHDSL emulating E1 payloads.
While the cell delineation state machine is in the SYNC state, the verification circuit implements the state machine
shown in Figure 8.
SHDSL E1
SHDSL T1
Format
Consecutive
Incorrect HEC
(cell by cell)
ALPHA
Figure 7 - Cell Delineation State Diagram
HUNT
Table 3 - Cell Acquisition Time
Zarlink Semiconductor Inc.
ZL30226/7/8
Valid HEC (byte by byte)
Incorrect HEC
(cell by cell)
Average Cell Time (µs)
SYNC
43
276
221
DELTA Consecutive
Correct HEC
(cell by cell)
PRESYNC
Data Sheet
.