ZL30226/GA ZARLINK [Zarlink Semiconductor Inc], ZL30226/GA Datasheet - Page 48

• Manufacturer Part Number: ZL30226/GA
• Description: 4/8/16 Port IMA/TC PHY Device for xDSL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

During the start-up phase, the software can choose to collect all valid ICP cells from a RX TDM port and determine
if the parameters are acceptable to proceed to start-up an IMA group.
In normal IMA operating mode, the software will choose to collect only valid ICP cells with changes. The Status and
Control Change Indication (SCCI) is monitored for all valid ICP cells received. If the SCCI field indicates a change
in the ICP cells, they are put aside for processing by software.
To accelerate the processing of ICP cells that contain changes, any byte of the last and next processed ICP cell can
be accessed directly. To reduce the total processing time by the software, only those bytes that need to be read are
accessed. The storage unit keeps the last read ICP cell and has room for up to three new ICP cells.
3.3.10
The ZL30226/7/8 computes the internal RX IMA Data Cell Rate (IDCR) for each IMA Group. The cell rate of the
reference link is integrated over a programmable period of time. Software must specify the reference link for the IMA
Group in the RX Reference Link Control (0x0209 - 0x0210) registers and the period of integration in the RX IDCR
Integration (0x0219 - 0x021C) registers. Refer to TX IMA Data Cell Rate in Section 2.4.5. The Rx Preprocessor is
also available to aid the comparison of cells. See section 6.4.
As an option, the number of the link to be used as a reference link can be extracted automatically from octet 14 of
the received ICP cell. This option is selected by bit 4 of the RX Reference Link Control (0x0209 - 0x0210) registers.
3.3.11
The received cells are temporarily stored in external memory buffers until they can be correctly re-ordered for output.
Memory size depends on the number of links and the maximum delay allowed between the links. The memory
requirements for different configurations are listed in Table 4:
The memory is organized in blocks of 64 bytes. Each block can hold one cell. The following equation can be used
to determine the maximum delay value or the required RAM size for a determined delay:
To simplify the RAM interface and pin loading, the ZL30226/7/8 supports the following six, register selectable,
external memory configurations:
•
•
•
•
•
•
one 32 KByte SRAM device
two 32 KByte SRAM devices
one 128 KByte SRAM device
two 128 KByte SRAM devices
one 512 KBytes SRAM device
two 512 KBytes SRAM devices.
Cell Buffer/RAM Controller
Rate Recovery
MaxDelay =
Zarlink Semiconductor Inc.
ZL30226/7/8
[RAMsize]
64
48
(16)
1
[1 CellTime]
Data Sheet