MT9072AV ZARLINK [Zarlink Semiconductor Inc], MT9072AV Datasheet - Page 155

• Manufacturer Part Number: MT9072AV
• Description: Octal T1/E1/J1 Framer
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Bit
12
10
11
9
8
7
6
5
4
3
2
1
0
F3SVS
F2HVS
F2EVS
F2RVS
F2SVS
F1HVS
F1EVS
F1RVS
F1SVS
F0HVS
F0EVS
F0RVS
F0SVS
Name
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Table 124 - Interrupt Vector 1 Status Register (Address 910) (T1) (continued)
Framer 3 Sync Vector Status. This bit if unmasked is set if any of the bits in the Interrupt Sync
status register(334) for Framer 3 are set. This bit can be masked and will remain low by the
F3SM bit in address 902.
Framer 2 HDLC Vector Status. This bit if unmasked is set if any of the bits in the Interrupt HDLC
register(233) or Elastic store status far Framer 2 are set. This bit can be masked and will remain
low by the F2HM bit in address 902.
Framer 2 Elastic Vector Status. This bit if unmasked is set if any of the bits in the Interrupt
Receive Elastic status register(236) or Elastic store status for Framer 2 are set. This bit can be
masked and will remain low by the F2EM bit in address 902.
Framer 2 Rx Line Vector Status. This bit if unmasked is set if any of the bits in the Interrupt
Receive Line status register(235) for Framer 2 are set. This bit can be masked and will remain
low by the F2RM bit in address 902.
Framer 2 Sync Vector Status. This bit if unmasked is set if any of the bits in the Interrupt
Counter status register(234) for Framer 2 are set. This bit can be masked and will remain low by
the F2SM bit in address 902.
Framer 1 HDLC Vector Status. This bit if unmasked is set if any of the bits in the Interrupt HDLC
register(133) or Elastic store status for Framer 1 are set. This bit can be masked and will remain
low by the F2HM bit in address 902.
Framer 1 Elastic Vector Status. This bit if unmasked is set if any of the bits in the Interrupt
Receive Elasitc store register(136) or Elastic store status for Framer 1 are set. This bit can be
masked and will remain low by the F1EM bit in address 902.
Framer 1 Rx Line Vector Status. This bit if unmasked is set if any of the bits in the Interrupt
Receive Line status register(135) for Framer 1 are set. This bit can be masked and will remain
low by theF1RM bit in address 902.
Framer 1 Sync Vector Status. This bit if unmasked is set if any of the bits in the Interrupt Sync
status register(134) for Framer 3 are set. This bit can be masked and will remain low by the
F1SM bit in address 902.
Framer 0 HDLC Vector Status. This bit if unmasked is set if any of the bits in the Interrupt HDLC
register(033) or Elastic store status for Framer 0 are set. This bit can be masked and will remain
low by the F0HM bit in address 902.
Framer 0 Elastic Vector Status. This bit if unmasked is set if any of the bits in the Interrupt
Receive Elasitc store register(036) or Elastic store status for Framer 0 are set. This bit can be
masked and will remain low by the F0EM bit in address 902.
Framer 0 Rx Line Vector Status. This bit if unmasked is set if any of the bits in the Interrupt
Receive Line status register(035) for Framer 0 are set. This bit can be masked and will remain
low by the F0RM bit in address 902.
Framer 0 Sync Vector Status. This bit if unmasked is set if any of the bits in the Interrupt Sync
status register(034) for Framer 0 are set. This bit can be masked and will remain low by the
F0SM bit in address 902.
Zarlink Semiconductor Inc.
MT9072
Functional Description
155
Data Sheet