MT9072AV ZARLINK [Zarlink Semiconductor Inc], MT9072AV Datasheet - Page 190

• Manufacturer Part Number: MT9072AV
• Description: Octal T1/E1/J1 Framer
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Bit
15
14
13
12
11
10
Table 163 - Frame Alignment Signal (FAS) Bit Error Counter & FAS Error Counter (R/W Address Y1A)
9
8
7
6
5
4
3
2
1
0
15-12
7 - 0
Bit
10
11
9
8
Name
BEC7
BEC6
BEC5
BEC4
BEC3
BEC2
BEC1
BEC0
FEC7
FEC6
FEC5
FEC4
FEC3
FEC2
FEC1
FEC0
TBP7-0
Name
RXclk
TXclk
Vaddr
####
Vcrc
Table 164 - Transmit Byte Counter Position and HDLC Test Status(Y1C) (E1)
Frame Alignment Signal (FAS) Bit Error Counter. These bits make up a counter which is
incremented for each individual error in the received PCM30 link basic frame alignment signal
(FAS) pattern (x0011011 in timeslot 0 of alternate frames). This counter is cleared with an
overflow, a RESET (RESET pin or RST bit), or it may be set by writing the desired value to it.
BEC0 is the least significant bit (LSB). The lower byte and upper byte of register cannot be written
to independently.
Frame Alignment Signal (FAS) Error Counter. These bits make up a counter which is
incremented for each combined (one or more) error in the received PCM30 link basic frame
alignment signal (FAS) pattern (x0011011 in timeslot 0 of alternate frames). This counter is
cleared with an overflow, a RESET (RESET pin or RST bit), or it may be set by writing the desired
value to it. FEC0 is the least significant bit (LSB). The lower byte and upper byte of register
cannot be written to independently.
not used.
This bit represents the receiver clock generated after the RXEN control bit, but before
zero deletion is considered.
This bit represents the transmit clock generated after the TXEN control bit, but before
zero insertion is considered.
This is the CRC recognition status bit for the receiver. Data is clocked into the register and
then this bit is monitored to see if comparison was successful (bit will be high).
This is the address recognition status bit for the receiver. Data is clocked into the Address
Recognition Register and then this bit is monitored to see if comparison was successful
(bit will be high).
Transmit Byte Counter Position. These 7 bits provide the position of the Transmit HDLC
Byte Counter register (YF6). The counter is decremented as a byte of data is sent through
the Transmit FIFO.
When this register reaches the count of one, the next write to the Tx FIFO will be tagged
as an end of packet byte. The counter decrements at the end of the write to the Tx FIFO.
If the Cycle bit of YF2 is set high, the counter will cycle through the programmed value
continuously.
Zarlink Semiconductor Inc.
MT9072
Functional Description
(E1)
190
Functional Description
Data Sheet