MT9072AV ZARLINK [Zarlink Semiconductor Inc], MT9072AV Datasheet - Page 203
MT9072AV
Manufacturer Part Number
MT9072AV
Description
Octal T1/E1/J1 Framer
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.MT9072AV.pdf
(275 pages)
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Table 180 - CAS, National, CRC-4 Local and Timer Interrupt Status Register (Address Y36) (E1)
Sa6N8I
Sa6V3I
Sa6V2I
Sa6V1I
Sa6V0I
CASRI
CALNI
Name
Sa5VI
Sa6NI
Sa5TI
SaNI
SaTI
#
not used.
Sa5 Value Bit Interrupt. This bit is one when the corresponding latched status bit (Sa5VL,
register address Y26) is set, and the corresponding mask bit is unmasked (Sa5VM, register
address Y46). This bit is cleared when either this register, or the latched status register is read.
Sa6 Value Bits 3-0 Interrupt. This bit is one when the corresponding latched status bit
(Sa6V*L, register address Y26) is set, and the corresponding mask bit is unmasked (Sa6V*M,
register address Y46). This bit is cleared when either this register, or the latched status register
is read.
Eight Consecutive Sa6 Nibbles Interrupt. This bit is one when the corresponding latched
status bit (Sa6N8L, register address Y26) is set, and the corresponding mask bit is unmasked
(Sa6N8M, register address Y46). This bit is cleared when either this register, or the latched
status register is read.
Sa6 Nibble Change Interrupt. This bit is one when the corresponding latched status bit
(Sa6NL, register address Y26) is set, and the corresponding mask bit is unmasked (Sa6NM,
register address Y46). This bit is cleared when either this register, or the latched status register
is read.
Sa Nibble Change Interrupt. This bit is one when the corresponding latched status bit (SaNL,
register address Y26) is set, and the corresponding mask bit is unmasked (SaNM, register
address Y46). This bit is cleared when either this register, or the latched status register is read.
Sa5 Bit Change Interrupt. This bit is one when the corresponding latched status bit (Sa5TL,
register address Y26) is set, and the corresponding mask bit is unmasked (Sa5TM, register
address Y46). This bit is cleared when either this register, or the latched status register is read.
Sa Bit Change Interrupt. This bit is one when the corresponding latched status bit (SaTL,
register address Y26) is set, and the corresponding mask bit is unmasked (SaTM, register
address Y46). This bit is cleared when either this register, or the latched status register is read.
Receive Channel Associated Signaling (CAS) Interrupt. is bit is one when the
corresponding latched status bit (CASRL, register address Y24) is set, and the corresponding
mask bit is unmasked (CASRM, register address Y44). This bit is cleared when either this
register, or the latched status register is read.
CRC-4 Alignment 2 ms Timer Interrupt. This bit is one when the corresponding latched
status bit (CALNL, register address Y26) is set, and the corresponding mask bit is unmasked
(CALNM, register address Y46). This bit is cleared when either this register, or the latched
status register is read.
Zarlink Semiconductor Inc.
MT9072
Functional Description
203
Data Sheet
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