ZL50017GAC ZARLINK [Zarlink Semiconductor Inc], ZL50017GAC Datasheet
ZL50017GAC
Related parts for ZL50017GAC
ZL50017GAC Summary of contents
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... Input Timing MODE_4M0 MODE_4M1 Figure 1 - ZL50017 Functional Block Diagram Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved. Ordering Information ZL50017GAC ZL50017QCC ZL50017GAG2 **Pb Free Tin/Silver/Copper • Connection memory block programming • ...
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Description The ZL50017 is a maximum 1024 x 1024 channel non-blocking digital Time Division Multiplex (TDM) switch. It has sixteen input streams (STi0 - 15) and sixteen output streams (STio0 - 15). The device can switch 64 kbps and Nx64 ...
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Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 1 - ZL50017 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 1 - Delay for Variable Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Changes Summary The following table captures the changes from the October 2004 issue. Page Item 13 Pin Description “STio 0 - 15” on page 13 ZL50017 • Clarified STio 0-15 pin description. 6 Zarlink Semiconductor Inc. Data Sheet Change ...
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Pinout Diagrams 1.1 BGA Pinout STi10 STi5 STi4 STi9 V STi7 STi6 STi11 V STi3 STi2 DD_IO E NC ...
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QFP Pinout 192 190 188 186 184 182 180 178 NC NC 194 VDD_IO NC 196 NC STi_8 198 VSS STi_9 200 STi_10 STi_11 202 STi_12 STi_13 204 STi_14 STi_15 206 VDD_IO IC_GND 208 VSS IC_Open 210 RESET TDo ...
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Pin Description PBGA Pin LQFP Pin Pin Name Number Number E6, E11, F6, 19, 33, V DD_CORE F7, F10, 45, 83, F11, L6, L7, 95, 109, L10, L11, 146, 173, M6, M7, 213, 233 M10, M11 H4, K5, B9, ...
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PBGA Pin LQFP Pin Pin Name Number Number K3 234 TMS L4 238 TCK L3 239 TRST M3 240 TDi G5 212 TDo B12, B13, 80, 105, IC_Open C10, C11, 150, 151, F13, G4, 152, 153, K12, C12, 210, 149 ...
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PBGA Pin LQFP Pin Pin Name Number Number A8, A9, A14, 61, 62, NC A15, E10, 63, 64, M2, N2, P2, 65, 66, P16, R2, 67, 68, R16, T6, T7, 134, 135, T8, T9, T10, 136, 137, T11, T12, 138, ...
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PBGA Pin LQFP Pin Pin Name Number Number M14, R13 46, 48 MODE_4M0, MODE_4M1 B10 155 FPi B11 154 CKi B6, C6, D5, 179, 180, STi0 - 15 D4, B4, B3, 181, 182, C5, C4, E3, 183, 184, C2, B2, ...
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PBGA Pin LQFP Pin Pin Name Number Number N4, P4, R4 STio P5, N13, 10, 51, P11, R14, 52, 53, R15, M15, 54, 70, L15, L13, 72, 73, L14, E14, 74, 115, D13, D15, ...
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PBGA Pin LQFP Pin Pin Name Number Number K13, K15, 82, 84 K14, J11, 86, 87, J12, J13, 88, 89, J15, H11, 90, 91, J14, H12, 92, 93, H13, H15, 94, 96, G12, G13 98, 99 M13 ...
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The output streams can be programmed to operate as bi-directional streams. By setting BDL (bit 6) in the Internal Mode Selection (IMS) register, the input streams (STi0 - 15) are internally tied low, and the output streams ...
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FPi (122 ns) FPINP = 0 FPINPOS = 0 FPi (122 ns) FPINP = 1 FPINPOS = 0 FPi (122 ns) FPINP = 0 FPINPOS = 1 FPi (122 ns) FPINP = 1 FPINPOS = 1 CKi (8.192 MHz) CKINP ...
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ST-BUS and GCI-Bus Timing The ZL50017 is capable of operating using either the ST-BUS or GCI-Bus standards. By default, the ZL50017 is configured for ST-BUS input and output timing. To set the input timing to conform to the GCI-Bus ...
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Input Bit Delay Programming The input bit delay programming feature provides users with the flexibility of handling different wire delays when designing with source streams for different devices. By default, all input streams have zero bit delay, such that ...
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Input Bit Sampling Point Programming In addition to the input bit delay feature, the ZL50017 allows users to change the sampling point of the input bit by programming STIN[n]SMP 1-0 (bits the Stream Input Control ...
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The input delay is controlled by STIN[n]BD2-0 (bits control the bit shift and STIN[n]SMP1 - 0 (bits control the sampling point in the Stream Input Control Register (SICR0 - ...
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FPi Last Channel STio[ Bit Adv = 0 (Default) Last Channel STio[ Bit Adv = 1 Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and ...
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Data Delay Through the Switching Paths The switching of information from the input serial streams to the output serial streams results in a throughput delay. The device can be programmed to perform timeslot interchange functions with different throughput delay ...
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Constant Delay Mode In this mode, frame integrity is maintained in all switching configurations. The delay though the switch is 2 frames - Input Channel + Output Channel. This can result in a minimum of 1 frame + 1 ...
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Connection Memory Block Programming This feature allows for fast initialization of the connection memory after power up. 8.1 Memory Block Programming Procedure 1. Set MBPE (bit 3) in the Control Register (CR) from low to high. 2. Configure BPD2 ...
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Device Reset and Initialization The RESET pin is used to reset the ZL50017. When this pin is low, the following functions are performed: • synchronously puts the microprocessor port in a reset state • tristates the STio0 - 15 ...
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Test Mode Selection Inputs (TMS) - The TAP Controller uses the logic signals received at the TMS input to control test operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally ...
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Register Address Mapping Address CPU A13 - A0 Access 0000 R/W Control Register H 0001 R/W Internal Mode Selection Register H 0002 R/W Software Reset Register H 0008 R/W Data Rate Selection Register H 0010 R Only Internal Flag ...
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Detailed Register Description External Read/Write Address: 0000 H Reset Value: 0000 Bit Name Unused Reserved. In normal functional mode, these bits MUST be set to ...
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External Read/Write Address: 0000 H Reset Value: 0000 Bit Name 2 OSB Output Stand By Bit: This bit enables the STio0 - 1 serial outputs. The following table describes ...
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External Read/Write Address: 0001 H Reset Value: 0000 Bit Name Unused Reserved. In normal functional mode, these bits MUST be set to zero. 8 ...
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External Read/Write Address: 0002 H Reset Value: 0000 Bit Name Unused Reserved In normal functional mode, these bits MUST be set to zero. 1 SRSTSW Software ...
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External Read Address: 0010 H Reset Value: 0000 Bit Name Unused Reserved In normal functional mode, these bits are zero. 0 PERR Program Error (Read Only) ...
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External Read/Write Address: 0100 - 010F H H Reset Value: 0000 Bit Name 0 STIN[n]EN Input Stream Enable Bit When this bit is high the ...
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Memory 14.1 Memory Address Mappings When A13 is high, the data or connection memory can be accessed by the microprocessor port. Bit the Control Register determine the access to the data or connection memory (CM_L ...
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Connection Memory Low (CM_L) Bit Assignment When the CMM bit (bit 0) in the connection memory low is zero, the per-channel transmission is set to the normal channel-switching. The connection memory low bit assignment for the channel transmission mode ...
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When CMM is one, the device is programmed to perform one of the special per-channel transmission modes. Bits PCC0 and PCC1 from connection memory are used to select the per-channel tristate or message mode as shown in Table 13 on ...
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DC Parameters Absolute Maximum Ratings* Parameter 1 I/O Supply Voltage 2 Core Supply Voltage 3 Input Voltage 4 Input Voltage (5 V-tolerant inputs) 5 Continuous Current at Digital Outputs 6 Package Power Dissipation 7 Storage Temperature * Exceeding these ...
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AC Parameters † AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels Characteristics 1 CMOS Threshold 2 Rise/Fall Threshold Voltage High 3 Rise/Fall Threshold Voltage Low † Characteristics are over recommended operating conditions unless otherwise stated. ALL SIGNALS Figure ...
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AC Electrical Characteristics - Motorola Non-Multiplexed Bus Mode - Read Access Characteristics 1 CS de-asserted time 2 DS de-asserted time 3 CS setup to DS falling 4 R/W setup to DS falling 5 Address setup to DS falling 6 ...
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AC Electrical Characteristics - Motorola Non-Multiplexed Bus Mode - Write Access Characteristics 1 CS de-asserted time 2 DS de-asserted time 3 CS setup to DS falling 4 R/W setup to DS falling 5 Address setup to DS falling 6 ...
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AC Electrical Characteristics - Intel Non-Multiplexed Bus Mode - Read Access Characteristics 1 CS de-asserted time 2 RD setup to CS falling 3 WR setup to CS falling 4 Address setup to CS falling 5 RD hold after CS ...
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AC Electrical Characteristics - Intel Non-Multiplexed Bus Mode - Write Access Characteristics 1 CS de-asserted time 2 WR setup to CS falling 3 RD setup to CS falling 4 Address setup to CS falling 5 Data setup to CS ...
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AC Electrical Characteristics - JTAG Test Port Timing Characteristic 1 TCK Clock Period 2 TCK Clock Pulse Width High 3 TCK Clock Pulse Width Low 4 TMS Set-up Time 5 TMS Hold Time 6 TDi Input Set-up Time 7 ...
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AC Electrical Characteristics - FPi and CKi Timing when CKIN1-0 bits = 00 (16.384 MHz) Characteristic 1 FPi Input Frame Pulse Width 2 FPi Input Frame Pulse Setup Time 3 FPi Input Frame Pulse Hold Time 4 CKi Input ...
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AC Electrical Characteristics - FPi and CKi Timing when CKIN1-0 bits = 10 (4.096 MHz) Characteristic 1 FPi Input Frame Pulse Width 2 FPi Input Frame Pulse Setup Time 3 FPi Input Frame Pulse Hold Time 4 CKi Input ...
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AC Electrical Characteristics - ST-BUS/GCI-Bus Input Timing Characteristic 1 STi Setup Time 2.048 Mbps 4.096 Mbps 8.192 Mbps 16.384 Mbps 2 STi Hold Time 2.048 Mbps 4.096 Mbps 8.192 Mbps 16.384 Mbps 3 STio Delay - Active to Active ...
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FPi CKi (16.384 MHz) FPi CKi (8.192 MHz) FPi CKi (4.096 MHz) STi0 - 15 Bit0 2.048 Mbps Ch31 STi0 - 15 Bit0 4.096 Mbps Ch63 STi0 - 15 Bit1 Bit0 Bit7 Ch127 Ch127 Ch0 8.192 Mbps Input Frame Boundary ...
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FPi CKi (16.384 MHz) FPi CKi (8.192 MHz) FPi CKi (4.096 MHz) STi0 - 15 Bit7 2.048 Mbps Ch31 STi0 - 15 Bit7 4.096 Mbps Ch63 STi0 - 15 Bit6 Bit7 Bit0 Ch127 Ch127 Ch0 8.192 Mbps Input Frame Boundary ...
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Zarlink Semiconductor 2003 All rights reserved. 1 ISSUE 214440 ACN 26June03 DATE APPRD. Package Code Previous package codes ...
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Zarlink Semiconductor 2003 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
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