ZL50017GAC ZARLINK [Zarlink Semiconductor Inc], ZL50017GAC Datasheet - Page 19

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ZL50017GAC

Manufacturer Part Number
ZL50017GAC
Description
1 K Digital Switch
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
5.2
In addition to the input bit delay feature, the ZL50017 allows users to change the sampling point of the input bit by
programming STIN[n]SMP 1-0 (bits 5 - 4) in the Stream Input Control Register 0 - 15 (SICR0 - 15). For input
streams the default sampling point is at 3/4 bit and users can change the sampling point to 1/4, 1/2, 3/4 or 4/4 bit
position.
STi[n]
STIN[n]SMP1-0 = 00
2, 4 or 8 Mbps - Default
FPi
STi[n]
STIN[n]SMP1-0 = 01
(2, 4 or 8 Mbps)
STi[n]
STIN[n]SMP1-0 = 10
2, 4 or 8 Mbps
STIN[n]SMP1-0 = 00
16 Mbps - Default
STi[n]
STIN[n]SMP1-0 = 11
2, 4 or 8 Mbps
STIN[n]SMP1-0 = 10
16 Mbps
Input Bit Sampling Point Programming
Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 Mbps mode respectively
2
Last Channel
Figure 8 - Input Bit Sampling Point Programming
2
1
Last Channel
Last Channel
Last Channel
1
1
Zarlink Semiconductor Inc.
1
ZL50017
0
0
19
0
0
7
7
7
Sampling Point = 1/4 Bit
7
Sampling Point = 1/2 Bit
6
Sampling Point = 3/4 Bit
6
Sampling Point = 4/4 Bit
Channel 0
Channel 0
Channel 0
Channel 0
6
6
5
5
5
5
Data Sheet

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