ZL50017GAC ZARLINK [Zarlink Semiconductor Inc], ZL50017GAC Datasheet - Page 28

• Manufacturer Part Number: ZL50017GAC
• Description: 1 K Digital Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

13.0
15 - 10
6 - 5
External Read/Write Address: 0000
Reset Value: 0000
Bit
9
8
7
4
3
15
0
Detailed Register Description
14
FPINPOS
CKIN1 - 0
0
Unused
VAREN
CKINP
FPINP
MBPE
Name
H
13
0
Reserved. In normal functional mode, these bits MUST be set to zero.
Input Frame Pulse (FPi) Position
When this bit is low, FPi straddles frame boundary (as defined by ST-BUS).
When this bit is high, FPi starts from frame boundary (as defined by GCI-Bus)
Clock Input (CKi) Polarity
When this bit is low, the CKi falling edge aligns with the frame boundary.
When this bit is high, the CKi rising edge aligns with the frame boundary.
Frame Pulse Input (FPi) Polarity
When this bit is low, the input frame pulse FPi has the negative frame pulse format.
When this bit is high, the input frame pulse FPi has the positive frame pulse format.
Input Clock (CKi) and Frame Pulse (FPi) Selection
The MODE_4M0 and MODE_4M1 pins, as described in “Pin Description” on page 9,
should also be set to define the input clock mode.
Variable Delay Mode Enable
When this bit is low, the variable delay mode is disabled on a device-wide basis.
When this bit is high, the variable delay mode is enabled on a device-wide basis.
Memory Block Programming Enable
When this bit is high, the connection memory block programming mode is enabled to
program the connection memory. When it is low, the memory block programming mode is
disabled.
12
0
H
11
0
Table 4 - Control Register (CR) Bits
10
0
CKIN1 - 0
00
01
10
11
FPIN
POS
Zarlink Semiconductor Inc.
9
ZL50017
CKINP
8
28
FPi Active Period
FPINP
7
Description
122 ns
244 ns
61 ns
CKIN
6
1
Reserved
CKIN
5
0
VAR
EN
4
16.384 MHz
8.192 MHz
4.096 MHz
MBPE
CKi
3
OSB
2
Data Sheet
MS1
1
MS0
0