ZL50021GAC ZARLINK [Zarlink Semiconductor Inc], ZL50021GAC Datasheet
ZL50021GAC
Related parts for ZL50021GAC
ZL50021GAC Summary of contents
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... France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08 Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved. Enhanced 4 K Digital Switch with Ordering Information ZL50021GAC ZL50021QCC ZL50021GAG2 **Pb Free Tin/Silver/Copper • Programmable key DPLL parameters (filter corner ...
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Per-stream input and output data rate conversion selection at 2.048, 4.096, 8.192 or 16.384 Mbps. Input and output data rates can differ • Per-stream high impedance control outputs (STOHZ) for output streams • Per-stream input bit ...
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Description The ZL50021 is a maximum 4,096 x 4,096 channel non-blocking digital Time Division Multiplex (TDM) switch. It has thirty-two input streams (STi0 - 31) and thirty-two output streams (STio0 - 31). The device can switch 64 kbps and Nx64 ...
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Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Lock Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 1 - ZL50021 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 49 - Output Timing (ST-BUS Format ...
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Table 1 - CKi and FPi Configurations for Master and Divided Slave Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 49 - Multi-period Far Lower Limit Register - Upper 16 Bits (MPFLLRU ...
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Changes Summary The following table captures the changes from the October 2004 issue. Page Item 39, 77, 79 Section 12.1, “DPLL Timing Modes“ on page 39 RCCR Register bits “FDM1 - 0” on page 77 RCSR Register bits “DPM1 - ...
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Pinout Diagrams 1.1 BGA Pinout STi29 STi28 STi27 STi25 SS B STi31 STi10 STi5 STi4 CKo2 C STi30 STi9 V STi7 STi6 SS D STi17 STi11 V STi3 STi2 DD_IO E STi16 ...
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QFP Pinout 192 190 188 186 184 182 180 178 STi28 STi29 194 VDD_IO STi30 196 STi31 STi_8 198 VSS STi_9 200 STi_10 STi_11 202 STi_12 STi_13 204 STi_14 STi_15 206 VDD_IO IC_GND 208 VSS IC_OPEN 210 RESET TDo ...
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Pin Description PBGA Pin LQFP Pin Pin Name Number Number E6, E11, F6, 19, 33, V DD_CORE F7, F10, 45, 83, F11, L6, L7, 95, 109, L10, L11, 146, 173, M6, M7, 213, 233 M10, M11 H4, K5, B9, ...
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PBGA Pin LQFP Pin Pin Name Number Number K3 234 TMS L4 238 TCK L3 239 TRST M3 240 TDi G5 212 TDo B12, B13, 80, 105, IC_OPEN C10, C11, 150, 151, F13, G4, 152, 153, K12 210 C13, G3 ...
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PBGA Pin LQFP Pin Pin Name Number Number D12 107 OSC_EN C12 149 OSCo B14 148 OSCi E9, D8, B8, 161, 164, REF0 - 3 D7 166, 168 D9, E8, C8, 159, 163, REF_FAIL0 - 3 E7 165, 167 ZL50021 ...
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PBGA Pin LQFP Pin Pin Name Number Number G15, G14, 102, 106, FPo0 - 3 E15, F14 110, 112 H14, D11 100, 104 FPo_OFF0 - 1 F15 108 FPo_OFF2 or FPo5 B7, C7, B5, 170, 172, CKo0 - 5 J6, ...
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PBGA Pin LQFP Pin Pin Name Number Number B10 155 FPi B11 154 CKi ZL50021 Description ST-BUS/GCI-Bus Frame Pulse Schmitt-Triggered Input) This pin accepts the frame pulse which stays active for 61 ns, 122 ns or 244 ns at the ...
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PBGA Pin LQFP Pin Pin Name Number Number B6, C6, D5, 179, 180, STi0 -31 D4, B4, B3, 181, 182, C5, C4, E3, 183, 184, C2, B2, D2, 185, 187, F3, F4, E2, 198, 200, F2, E1, D1, 201, 202, ...
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PBGA Pin LQFP Pin Pin Name Number Number B15 141 ODE M4, N6, R6, 16, 18 P7, R7, N7, 20, 22, M8, N8, P8, 23, 24, R8, M9, N9, 25, 26, R9, N10, P9, 27, 28, R10 ...
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PBGA Pin LQFP Pin Pin Name Number Number M13 41 MOT_INTEL P10 43 G2 211 RESET 3.0 Device Overview The device has thirty-two ST-BUS/GCI-Bus inputs (STi0 - 31) and thirty-two ST-BUS/GCI-Bus outputs (STio0 - 31). STio0 - 31 can also ...
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CKi can drive. For example, if CKi is 4.096 MHz, the output data rate cannot be higher than 2.048 Mbps. The second slave mode is called ...
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CKIN1 - 0 (bits the Control Register (CR) to indicate the width of the input frame pulse and the frequency of the input clock supplied to the device. In Master mode and Divided ...
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FPi (244 ns) FPINP = 0 FPINPOS = 0 FPi (244 ns) FPINP = 1 FPINPOS = 0 FPi (244 ns) FPINP = 0 FPINPOS = 1 FPi (244 ns) FPINP = 1 FPINPOS = 1 CKi (4.096 MHz) CKINP ...
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FPi (61 ns) FPINP = 0 FPINPOS = 0 FPi (61 ns) FPINP = 1 FPINPOS = 0 FPi (61 ns) FPINP = 0 FPINPOS = 1 FPi (61 ns) FPINP = 1 FPINPOS = 1 CKi (16.384 MHz) CKINP ...
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Pin Name FPo0 pulse width CKo0 FPo1 pulse width CKo1 FPo2 pulse width CKo2 FPo3 pulse width CKo3 CKo4 FPo5 pulse width CKo5 The output timing is dependent on the operation mode that is selected. When the device is in ...
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CKOFPO0EN = 1 FPO0P = 0 FPO0POS = 0 CKOFPO0EN = 1 FPO0P = 1 FPO0POS = 0 CKOFPO0EN = 1 FPO0P = 0 FPO0POS = 1 CKOFPO0EN = 1 FPO0P = 1 FPO0POS = 1 CKOFPO0EN = 1 CKO0P ...
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CKOFPO2EN = 1 FPO2P = 0 FPO2POS = 0 CKOFPO2EN = 1 FPO2P = 1 FPO2POS = 0 CKOFPO2EN = 1 FPO2P = 0 FPO2POS = 1 CKOFPO2EN = 1 FPO2P = 1 FPO2POS = 1 CKOFPO2EN = 1 CKO2P ...
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CKOFPO0EN = 1 FPO0P = 0 FPO0POS = 0 CKOFPO0EN = 1 FPO0P = 1 FPO0POS = 0 CKOFPO0EN = 1 FPO0P = 0 FPO0POS = 1 CKOFPO0EN = 1 FPO0P = 1 FPO0POS = 1 CKOFPO4EN = 1 CKO4P ...
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Data Input Delay and Data Output Advancement Various registers are provided to adjust the input delay and output advancement for each input and output data stream. The input bit delay and output bit advancement can vary from 0 to ...
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Input Bit Sampling Point Programming In addition to the input bit delay feature, the ZL50021 allows users to change the sampling point of the input bit by programming STIN[n]SMP 1-0 (bits the Stream Input Control ...
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The input delay is controlled by STIN[n]BD2-0 (bits control the bit shift and STIN[n]SMP1 - 0 (bits control the sampling point in the Stream Input Control Register (SICR0 - ...
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Output Advancement Programming This feature is used to advance the output data of individual output streams with respect to the output frame boundary. Each output stream has its own bit advancement value which can be programmed in the Stream ...
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Fractional Output Bit Advancement Programming In addition to the output bit advancement, the device has a fractional output bit advancement feature that offers better resolution. The fractional output bit advancement is useful in compensating for varying parasitic load on ...
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External High Impedance Control Advancement The external high impedance signals can be programmed to better match the timing required by the external buffers. By default, the output timing of the STOHZ signals follows the programmed channel delay and bit ...
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In variable delay mode, the delay depends on the combination of the source and destination channels of the input and output streams input channel number n = output channel number T = Delay between input and output For ...
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Frame N STi L-2 L-1 CH0 CH1 CH2 CH3 STio L-2 L-1 CH0 CH1 CH2 CH3 STi L-2 L-1 CH0 CH1 CH2 CH3 STio L-2 L-1 CH0 CH1 CH2 CH3 L = last channel = 31, 63, 127, or 255 ...
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Connection Memory Block Programming This feature allows for fast initialization of the connection memory after power up. 10.1 Memory Block Programming Procedure 1. Set MBPE (bit 3) in the Control Register (CR) from low to high. 2. Configure BPD2 ...
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CKi and FPi. Therefore, in Divided Slave mode, the output clock rates cannot exceed the CKi rate (the output data rates are also limited ...
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Divided Slave Mode Operation When the device is in Divided Slave mode, STio0 - 31 are driven by CKi. In this mode, the output streams and clocks have the same jitter characteristics as the input clock (CKi), but the ...
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Holdover Mode In holdover mode, the DPLL no longer synchronizes the output clock to any input reference. It maintains the frequency that it was at prior to entering holdover mode. The holdover mode typically happens when the input clock ...
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Free run Ref 0 failed Holdover 0 Ref 0 Ref 0 valid Holdover 3 Ref 3 Figure 21 - Automatic Reference Switching State Diagram with No Preferred Reference 12.1.3.2 Automatic Reference Switching With Preference If a particular reference needs to ...
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Option 1 Start Free run Preferred References: Ref 0 DPLL will switch between Ref 0 and Ref 1 Option 2 Start Free run Preferred References: Ref 1 DPLL will switch between Ref 1 and Ref 2 Option 3 Start Free ...
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With a preferred reference, if more than two references are required, or the two references are not in consecutive order, or the roles of the two references need to be interchanged, then external software is required to manually control the ...
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Input Frequencies Selection The input frequencies of REF can be automatically detected or programmed independently by the Reference Frequency Register (RFR) if RFRE (bit 1) in the DPLL Control Register (DPLLCR) is set. The detected frequency ...
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Input Jitter Acceptance The input jitter acceptance is specified in standards as the minimum amount of jitter of a certain frequency on the input clock that the DPLL must accept without making cycle slips or losing lock. The lower ...
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Fast Locking Mode If very fast locking feature (e.g., locking time in order desirable, the Bandwidth Control Register (BWCR) can be programmed to accommodate the feature for any selected corner frequency. In this mode, the ...
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Reference Upper Limit (in Frequency 10 ns units) 8 kHz ‘h2E4A 1.544 MHz ‘h002B 2.048 MHz ‘h0025 4.096 MHz ‘h0011 8.192 MHz ‘h0007 16.384 MHz ‘h0002 19.44 MHz ‘h0002 Table 12 - Default Values for Single Period Limits 15.7 Multiple ...
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Far Upper Limit Near Upper Limit Nominal Value Near Lower Limit Far Lower Limit 16.0 Microprocessor Port The device provides access to the internal registers, connection memories and data memories via the microprocessor port. The microprocessor port is capable of ...
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Device Initialization on Reset Upon power up, the should be initialized as follows: • Set the ODE pin to low to disable the STio0 - 31 outputs and to drive STOHZ0 - 15 to high • Set the TRST ...
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BER Receiver Error Register (BRER) - This read-only register contains the number of counted errors. When the error count reaches 0xFFFF, the BER counter will stop updating so that it will not overflow. ST[n]CBER (bit 1) in the BER ...
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Quadrant Frame Programming By programming the Stream Input Quadrant Frame Registers (SIQFR0 - 31), users can divide one frame of input data into four quadrant frames and can force the LSB or MSB of every input channel in these ...
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The received input data is sampled at the rising edge of the TCK pulse. This pin is internally pulled to high when it is not driven from an external source. • Test Data Output (TDo) ...
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Register Address Mapping 0000 R/W Control Register H 0001 R/W Internal Mode Selection Register H 0002 R/W Software Reset Register H 0003 R/W Output Clock and Frame Pulse Control Register H 0004 R/W Output Clock and Frame Pulse Selection ...
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R/W Multi-period Near Upper Limit Register - Upper 16 Bits H 0050 R/W Multi-period Far Upper Limit Register - Lower 16 Bits H 0051 R/W Multi-period Far Upper Limit Register - Upper 16 Bits H 0052 R/W Multi-period Near ...
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R/W Stream Input Quadrant Frame Registers 013F H 0200 - R/W Stream Output Control Registers 021F H 0300 - R/W BER Receiver Start Registers 031F H ...
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Detailed Register Description External Read/Write Address: 0000 H Reset Value: 0000 SLV_ OPM OPM DPLLEN 1 0 Bit Name Unused Reserved. In normal functional mode, these bits MUST ...
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External Read/Write Address: 0000 H Reset Value: 0000 SLV_ OPM OPM DPLLEN 1 0 Bit Name 4 VAREN Variable Delay Mode Enable When this bit is low, the variable delay mode is ...
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External Read/Write Address: 0001 H Reset Value: 0000 Bit Name Unused Reserved. In normal functional mode, these bits MUST be set to zero. 8 ...
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External Read/Write Address: 0001 H Reset Value: 0000 Bit Name 0 MBPS Memory Block Programming Start: A zero to one transition of this bit starts the memory ...
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External Read/Write Address: 0003 H Reset Value: 0000 Bit Name Unused Reserved. In normal functional mode, these bits MUST be set to zero. 8 ...
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External Read/Write Address: 0004 H Reset Value: 0000 CKO4 CKO4 CKO CKO CKO3 P SEL FPO3 FPO3 P SEL1 SEL0 Bit Name 15 CKO4P Output Clock (CKo4) Polarity Selection When this bit is low, ...
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External Read/Write Address: 0004 H Reset Value: 0000 CKO4 CKO4 CKO CKO CKO3 P SEL FPO3 FPO3 P SEL1 SEL0 Bit Name 6 FPO2POS Output Frame Pulse (FPo2) Position When this bit is low, ...
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External Read/Write Address: 0005 - 0007 H Reset Value: 0000 FP19 EN Bit Name Unused Reserved. In normal functional mode, these bits MUST be set ...
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External Read Address: 0010 H Reset Value: 0000 Bit Name Unused Reserved In normal functional mode, these bits are zero. 1 OUTERR Output Error (Read Only) ...
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External Read/Write Address: 00012 H Reset Value: 0000 BER BER BER BER BER F31 F30 F29 F28 F27 Bit Name BERF[n] BER Error Flag[n] If BERF[n] is high, it indicates that ...
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External Read Address: 00014 H Reset Value: 0000 BER BER BER BER BER L31 L30 L29 L28 L27 Bit Name BERL[n] BER Receiver Lock[n] If BERL[n] is high, it indicates that ...
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External Read/Write Address: 0040 H Reset Value: 0000 Bit Name 4 SWF Software Mode Fast Control Bit. When this bit is low, the SWE bit is high, and the ...
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External Read/Write Address: 0041 H Reset Value: 0000 R3F2 Bit Name 15-12 Unused Reserved In normal functional mode, these bits MUST be set to zero R3F2 - ...
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External Read/Write Address: 0041 H Reset Value: 0000 R3F2 Bit Name R1F2 - 0 Reference 1 Frequency Bits When the RFRE bit of the DPLLCR register is ...
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External Read/Write Address: 0042 H Reset Value: 16B1 CFN CFN CFN CFN CFN Bit Name CFN15 - 0 Center Frequency Number (CFN) Lower 16 Bits: The ...
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External Read/Write Address: 0043 H Reset Value: 029F Bit Name Unused Reserved. In normal functional mode, these bits MUST be set to zero ...
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External Read Only Address: 0045 FOF FOF FOF FOF Bit Name 15 Unused Reserved. In normal functional mode, this bit is zero FOF14 - 0 Frequency ...
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External Read/Write Address: 0047 H Reset Value: 000F LDT LDT LDT LDT LDT Bit Name LDT15 - 0 Lock Detect Threshold Bits: The binary value of ...
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External Read/Write Address: 0049 H Reset Value: 099F (see Note SRL SRL 12 11 Bit Name Unused Reserved. In normal functional mode, these bits MUST be set to ...
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External Read/Write Address: 004A H Reset Value: 0002 (see Note BLM FLF_ FLC QS 3 Bit Name FFL3 - 0 Fast Frequency Lock Bits: When the BLM bit in ...
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External Read/Write Address: 004B H Reset Value: 0000 Bit Name Unused Reserved. In normal functional mode, these bits MUST be set to zero. 7 MTR MTIE ...
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External Read/Write Address: 004B H Reset Value: 0000 Bit Name FDM1 - 0 Force DPLL Timing Mode: These bits force the DPLL into one of the ...
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External Read Only Address: 004C Bit Name Unused Reserved. In normal functional mode, these bits are zero. 8 SLM Slew Rate Limiter Status Bit: If the ...
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External Read Only Address: 004C Bit Name DPM1 - 0 DPLL Timing Mode Status Bits: These bits indicate the DPLL’s timing mode status. Table 41 - ...
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External Read/Write Address: 004F H Reset Value: 3B9A (Note MNU MNU MNU MNU MNU Bit Name MNU31 - 16 Multiple-Period Near Upper Limit Bits: Total ...
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External Read/Write Address: 0051 H Reset Value: 3B9A (Note MFU MFU MFU MFU MFU Bit Name MFU31 - 16 Multiple-Period Far Upper Limit Bits: Total ...
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External Read/Write Address: 0053 H Reset Value: 3B9A (Note MNL MNL MNL MNL MNL Bit Name MNL31 - 16 Multiple-Period Near Lower Limit Bits: Total ...
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External Read/Write Address: 0055 H Reset Value: 3B9A (Note MFL MFL MFL MFL MFL Bit Name MFL31 - 16 Multiple-Period Far Lower Limit Bits: Total ...
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External Read/Write Addresses: 0057 , 005B H Reset Value: 0001 (see Note MC[n] MC[n] MC[n] MC[n] MC[ Bit Name MC[n] Reference n Multi-period ...
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External Read/Write Addresses: 0058 , 005C H Reset Value: 2E4A (see Note UL[n] UL[n] UL[n] UL[n] UL[ Bit Name UL[n]15 - Reference n Single Period ...
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External Read/Write Addresses: 0059 , 005D H Reset Value: 335C (see Note LL[n] LL[n] LL[n] LL[n] LL[ Bit Name LL[n] Reference n Single ...
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External Read Only Address: 0066 Bit Name Unused Reserved. In normal functional mode, these bits is zero. 3 LCI Lock Change Interrupt Bit: If the device ...
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External Read/Write Address: 0067 H Reset Value: 000F Bit Name Unused Reserved. In normal functional mode, these bits MUST be set to zero. 3 LIM Lock ...
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External Read Only Address: 0069 FML FMU FL FU FML FMU Bit Name 15 R3FML Reference 3 Multi-period Lower Limit Fail Bit: If the device sets this bit to ...
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External Read Only Address: 0069 FML FMU FL FU FML Bit Name 6 R1FMU Reference 1 Multi-period Upper Limit Fail Bit: If the device sets this bit to high, ...
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External Read/Write Address: 006A H Reset Value: 0000 MML MMU ML MU MML MMU Bit Name 14 R3MMU Reference 3 Multi-period Upper Limit Mask Bit: When this bit is ...
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External Read Only Address: 006B R3FS 2 Bit Name Unused Reserved. In normal functional mode, these bits are zero R3FS2 - 0 Reference 3 ...
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External Read Only Address: 006B R3FS 2 Bit Name R1FS2 - 0 Reference 1 Frequency Status Bits: These bits report detected frequency of REF1. R1FS2 2 - ...
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External Read/Write Address: 006C H Reset Value: 0002 Bit Name Unused Reserved. In normal functional mode, these bits MUST be set to zero ...
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External Read/Write Address: 0100 - 011F H H Reset Value: 0000 Bit Name STIN[n]DR3 - 0 Input Data Rate Selection Bits: Note: ...
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External Read/Write Address: 0120 - 013F H H Reset Value: 0000 STIN[n] STIN[n] STIN[n] Q3C2 Q3C1 Q3C0 Bit Name Unused Reserved. In normal functional mode, these ...
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External Read/Write Address: 0120 - 013F H H Reset Value: 0000 STIN[n] STIN[n] Q3C2 Q3C1 Bit Name STIN[n]Q1C2 - 0 Quadrant Frame 1 Control Bits. These ...
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External Read/Write Address: 0200 - 021F H H Reset Value: 0000 STOHZ STOHZ [n]A2 [n]A1 Bit Name Unused Reserved. In normal functional mode, these bits MUST ...
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External Read/Write Address: 0300 - 031F H Reset Value: 0000 Bit Name Unused Reserved. In normal functional mode, these bits MUST be set to ...
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External Read/Write Address: 0340 - 035F H Reset Value: 0000 Bit Name Unused Reserved. In normal functional mode, these bits MUST be set to zero. 1 ...
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Memory 24.1 Memory Address Mappings When A13 is high, the data or connection memory can be accessed by the microprocessor port. Bit the Control Register determine the access to the data or connection memory (CM_L ...
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Connection Memory Low (CM_L) Bit Assignment When the CMM bit (bit 0) in the connection memory low is zero, the per-channel transmission is set to the normal channel-switching. The connection memory low bit assignment for the channel transmission mode ...
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When CMM is one, the device is programmed to perform one of the special per-channel transmission modes. Bits PCC0 and PCC1 from connection memory are used to select the per-channel tristate, message or BER test mode as shown in Table ...
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Connection Memory High (CM_H) Bit Assignment Connection memory high provides the detailed information required for µ-law and A-law conversion. ICL and OCL bits describe the Input Coding Law and the Output Coding Law, respectively. They are used to select ...
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Applications This section contains application-specific details for clock and crystal operation and power supply decoupling. 25.1 OSCi Master Clock Requirement The device requires a 20 MHz master clock source at the OSCi pin when operating in Master mode or ...
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External Clock Oscillator When an external clock oscillator is used, numerous parameters must be considered. They include absolute frequency, frequency change over temperature, output rise and fall times, output levels and duty cycle. The output clock should be connected ...
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DC Parameters Absolute Maximum Ratings* Parameter 1 I/O Supply Voltage 2 Core Supply Voltage 3 Input Voltage 4 Input Voltage (5V-tolerant inputs) 5 Continuous Current at Digital Outputs 6 Package Power Dissipation 7 Storage Temperature * Exceeding these values ...
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AC Parameters † AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels Characteristics 1 CMOS Threshold 2 Rise/Fall Threshold Voltage High 3 Rise/Fall Threshold Voltage Low † Characteristics are over recommended operating conditions unless otherwise stated. ALL SIGNALS Figure ...
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AC Electrical Characteristics - Motorola Non-Multiplexed Bus Mode - Read Access Characteristics 1 CS de-asserted time 2 DS de-asserted time 3 CS setup to DS falling 4 R/W setup to DS falling 5 Address setup to DS falling 6 ...
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AC Electrical Characteristics - Motorola Non-Multiplexed Bus Mode - Write Access Characteristics 14 CS de-asserted time 15 DS de-asserted time 16 CS setup to DS falling 17 R/W setup to DS falling 18 Address setup to DS falling 19 ...
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AC Electrical Characteristics - Intel Non-Multiplexed Bus Mode - Read Access Characteristics 27 CS de-asserted time 28 RD setup to CS falling 29 WR setup to CS falling 30 Address setup to CS falling 31 RD hold after CS ...
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AC Electrical Characteristics - Intel Non-Multiplexed Bus Mode - Write Access Characteristics 39 CS de-asserted time 40 WR setup to CS falling 41 RD setup to CS falling 42 Address setup to CS falling 43 Data setup to CS ...
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AC Electrical Characteristics - JTAG Test Port Timing Characteristic 1 TCK Clock Period 2 TCK Clock Pulse Width High 3 TCK Clock Pulse Width Low 4 TMS Set-up Time 5 TMS Hold Time 6 TDi Input Set-up Time 7 ...
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AC Electrical Characteristics - FPi and CKi Timing when CKIN1-0 bits = 00 (16.384 MHz) Characteristic 1 FPi Input Frame Pulse Width 2 FPi Input Frame Pulse Setup Time 3 FPi Input Frame Pulse Hold Time 4 CKi Input ...
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FPi t FPIS CKi Input Frame Boundary Figure 31 - Frame Pulse Input and Clock Input Timing Diagram (ST-BUS) FPi t FPIS CKi Input Frame Boundary Figure 32 - Frame Pulse Input and Clock Input Timing Diagram (GCI-Bus) ZL50021 t ...
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AC Electrical Characteristics - ST-BUS/GCI-Bus Input Timing Characteristic 1 STi Setup Time 2.048 Mbps 4.096 Mbps 8.192 Mbps 16.384 Mbps 2 STi Hold Time 2.048 Mbps 4.096 Mbps 8.192 Mbps 16.384 Mbps † Characteristics are over recommended operating conditions ...
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FPi CKi (16.384 MHz) t STi0 - 31 Bit1 Bit0 Bit7 Ch255 Ch255 Ch0 16.384 Mbps Input Frame Boundary Figure 34 - ST-BUS Input Timing Diagram when Operated at 16 Mbps FPi CKi (16.384 MHz) FPi CKi (8.192 MHz) FPi ...
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FPi CKi (16.384 MHz) t STi0 - 31 Bit6 Bit7 Bit0 Ch255 Ch255 Ch0 16.384 Mbps Input Frame Boundary Figure 36 - GCI-Bus Input Timing Diagram when Operated at 16 Mbps ZL50021 SIS16 t SIH16 Bit1 Bit2 Bit3 Bit4 Ch0 ...
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AC Electrical Characteristics - ST-BUS/GCI-Bus Master Mode Output Timing Characteristic 1 STio Delay - Active to Active at 2.048 Mbps at 4.096 Mbps at 8.192 Mbps at 16.384 Mbps † Characteristics are over recommended operating conditions unless otherwise stated. ...
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FPo0 CKo0 (4.096 MHz) STio0 - 31 Bit0 2.048 Mbps Ch31 STio0 - 31 Bit0 4.096 Mbps Ch63 t SOD8 STio0 - 31 Bit0 Bit7 8.192 Mbps Ch127 Ch0 t SOD16 STio0 - 31 Bit2 Bit1 Bit0 Bit7 Ch255 Ch255 ...
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AC Electrical Characteristics - ST-BUS/GCI-Bus Output Tristate Timing Characteristic 1 STio Delay - Active to High-Z 2 STio Delay - High-Z to Active 3 Output Drive Enable (ODE) Delay - High-Z to Active CKi @ 4.096 MHz CKi @ ...
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AC Electrical Characteristics - Slave Mode Input/Output Frame Boundary Alignment Characteristic 1 Input and Output Frame Offset in Divided Slave with CKi mode 2 Input and Output Frame Offset in Multiplied Slave † Characteristics are over recommended operating conditions ...
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FPo0/FPo3 CKo0/CKo3 Output Frame Boundary Figure 42 - FPo0 and CKo0 or FPo3 and CKo3 (4.096 MHz) Timing Diagram † AC Electrical Characteristics - FPo0 and CKo0 or FPo3 and CKo3 (4.096 MHz) Timing (Master Mode, Divided Slave Mode, or ...
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FPo1/FPo3 CKo1/CKo3 Output Frame Boundary Figure 43 - FPo1 and CKo1 or FPo3 and CKo3 (8.192 MHz) Timing Diagram † AC Electrical Characteristics - FPo1 and CKo1 or FPo3 and CKo3 (8.192 MHz) Timing (Master Mode, Divided Slave Mode, or ...
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FPo2/FPo3 CKo2/CKo3 Output Frame Boundary Figure 44 - FPo2 and CKo2 or FPo3 and CKo3 (16.384 MHz) Timing Diagram † AC Electrical Characteristics - FPo2 and CKo2 or FPo3 and CKo3 (16.384 MHz) Timing (Master Mode, Divided Slave Mode, or ...
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FPo3 CKo3 Output Frame Boundary Figure 45 - FPo3 and CKo3 (32.768 MHz) Timing Diagram † AC Electrical Characteristics - FPo3 and CKo3 (32.768 MHz) Timing (Master Mode, Divided Slave Mode, or Multiplied Slave Mode with less than 10 ns ...
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FPo0 CKo4 Output Frame Boundary Figure 46 - FPo4 and CKo4 Timing Diagram (1.544/2.048 MHz) † AC Electrical Characteristics - CKo4 (1.544 MHz) Timing (Only when DPLL is active) Characteristic 1 CKo4 Output Clock Period 2 CKo4 Output High Time ...
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FPo5 (shares output pin with FPo_OFF2) CKo5 Output Frame Boundary † AC Electrical Characteristics - CKo5 (19.44 MHz) Timing (Only when DPLL is active) Characteristic 1 FPo5 Output Pulse Width 2 FPo5 Output Delay from the FPo5 falling edge to ...
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AC Electrical Characteristics - REF0-3 Reference Input to CKo Output Timing Characteristic 1 Minimum input pulse width high or low 2 Input rise or fall time 3 Input to CKo0 output delay (no input jitter) with reference 8k, 2M, ...
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AC Electrical Characteristics - Master Mode Output Timing Characteristic 1 CKo0 to CKo1 (8.192 MHz) delay 2 CKo0 to CKo2 (16.384 MHz) delay 3 CKo0 to CKo3 (32.768 MHz/16.384 MHz/8.192 MHz/4.096 MHz) delay 4 CKo0 to CKo4 delay 2.048 ...
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FPo0 CKo0 (4.096 MHz) CKo4 (1.544 MHz) CKo1 (8.192 MHz) CKo2 (16.384 MHz) CKo5 (19.44 MHz) CKo3 (32.768 MHz) Figure 49 - Output Timing (ST-BUS Format) ZL50021 t C4D t C1D t C2D t C5D t C3D 131 Zarlink Semiconductor ...
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DPLL Performance Characteristics Characteristics 1 Freerun Mode accuracy 2 Initial Holdover Frequency Stability 3 Pull-in/Hold-in range (Stratum 3) 4 Reference Far Hysteresis Limit (Stratum 3) 5 Reference Near Hysteresis Limit (Stratum 3) 6 Output phase continuity for reference switch 7 ...
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Performance Characteristics Notes † Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25° and V DD_CORE testing. 1. Jitter on master clock input (XIN) is 100 ...
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Zarlink Semiconductor 2003 All rights reserved. 1 ISSUE 214440 ACN 26June03 DATE APPRD. Package Code Previous package codes ...
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Zarlink Semiconductor 2003 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
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For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in ...