ZL50021GAC ZARLINK [Zarlink Semiconductor Inc], ZL50021GAC Datasheet - Page 57

• Manufacturer Part Number: ZL50021GAC
• Description: Enhanced 4 K Digital Switch with Stratum 3 DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

1 - 0
External Read/Write Address: 0000
Reset Value: 0000
Bit
4
3
2
15
0
14
0
MS1 - 0
VAREN
MBPE
Name
OSB
DPLLEN
H
SLV_
13
Variable Delay Mode Enable
When this bit is low, the variable delay mode is disabled on a device-wide basis.
When this bit is high, the variable delay mode is enabled on a device-wide basis.
Memory Block Programming Enable
When this bit is high, the connection memory block programming mode is enabled to
program the connection memory. When it is low, the memory block programming mode is
disabled.
Output Stand By Bit
This bit enables the STio0 - 31 and the STOHZ0 -15 serial outputs. The following table
describes the HiZ control of the serial data outputs:
Note: Unused output streams are tristated (STio = HiZ, STOHZ = Driven High). Refer to
SOCR0 - 31 (bit2 - 0).
Memory Select Bits These two bits are used to select connection memory low, connec-
tion high or data memory for access by CPU:
OPM
12
1
Table 18 - Control Register (CR) Bits (continued)
RESET
H
OPM
Pin
11
0
1
1
1
1
0
MS1 - 0
CKi_
10
LP
00
01
10
11
SRSTSW
(in SRR)
X
1
0
0
0
FPIN
POS
Zarlink Semiconductor Inc.
9
ZL50021
CKINP
ODE
Pin
X
X
0
1
1
8
57
Connection Memory High Read/Write
Connection Memory Low Read/Write
FPINP
OSB
Bit
X
X
X
0
1
7
Description
Data Memory Read
Memory Selection
CKIN
6
1
(Controlled by CM)
Reserved
STio0 - 31
CKIN
Active
HiZ
HiZ
HiZ
HiZ
5
0
VAR
EN
4
MBPE
3
(Controlled by CM)
STOHZ0 - 15
Driven High
Driven High
Driven High
Driven High
OSB
Active
2
Data Sheet
MS1
1
MS0
0