ZL50021GAC ZARLINK [Zarlink Semiconductor Inc], ZL50021GAC Datasheet - Page 96

• Manufacturer Part Number: ZL50021GAC
• Description: Enhanced 4 K Digital Switch with Stratum 3 DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

15 - 12
External Read/Write Address: 0120
Reset Value: 0000
11 - 9
15
8 - 6
0
Bit
14
0
13
0
STIN[n]Q3C2 - 0
STIN[n]Q2C2 - 0
Table 62 - Stream Input Quadrant Frame Register 0 - 31 (SIQFR0 - 31) Bits
H
12
0
Unused
Name
STIN[n]
Q3C2
11
H
STIN[n]
- 013F
Q3C1
10
Reserved. In normal functional mode, these bits MUST be set to zero.
Quadrant Frame 3 Control Bits. These three bits are used to control STi[n]’s
quadrant frame 3, which is defined as Ch24 to 31, Ch48 to 63, Ch96 to 127 and
Ch192 to 255 for the 2.048 Mbps, 4.096 Mbps, 8.192 Mbps, and 16.384 Mbps
modes respectively.
Quadrant Frame 2 Control Bits. These three bits are used to control STi[n]’s
quadrant frame 2, which is defined as Ch16 to 23, Ch32 to 47, Ch64 to 95 and
Ch128 to 191 for the 2.048 Mbps, 4.096 Mbps, 8.192 Mbps, and 16.384 Mbps
modes respectively.
H
STIN[n]
Q3C0
9
STIN[n]Q3C
STIN[n]
Q2C2
Zarlink Semiconductor Inc.
8
STIN[n]Q2C
100
101
110
2-0
0xx
111
ZL50021
100
101
0xx
110
111
2-0
STIN[n]
Q2C1
7
96
STIN[n]
Q2C0
6
MSB of each channel is replaced by “0”
MSB of each channel is replaced by “1”
MSB of each channel is replaced by “0”
MSB of each channel is replaced by “1”
LSB of each channel is replaced by “0”
LSB of each channel is replaced by “1”
LSB of each channel is replaced by “0”
LSB of each channel is replaced by “1”
STIN[n]
Description
Q1C2
5
normal operation
normal operation
STIN[n]
Q1C1
4
Operation
Operation
STIN[n]
Q1C0
3
STIN[n]
Q0C2
2
STIN[n]
Q0C1
1
Data Sheet
STIN[n]
Q0C0
0