ZL50021GAC ZARLINK [Zarlink Semiconductor Inc], ZL50021GAC Datasheet - Page 21

• Manufacturer Part Number: ZL50021GAC
• Description: Enhanced 4 K Digital Switch with Stratum 3 DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

the input data rate, but the output data rate cannot be higher than what CKi can drive. For example, if CKi is
4.096 MHz, the output data rate cannot be higher than 2.048 Mbps. The second slave mode is called Multiplied
Slave mode. In this mode, CKi is used to generate a 16.384 MHz clock internally, and output streams are driven by
this 16.384 MHz clock. In Multiplied Slave mode, the data rate of output streams can be any rate, but output jitter
may not be exactly the same as input jitter.
A Motorola or Intel compatible non-multiplexed microprocessor port allows users to program the device to operate
in various modes under different switching configurations. Users can use the microprocessor port to perform
internal register and memory read and write operations. The microprocessor port has a 16-bit data bus, a 14-bit
address bus and six control signals (MOT_INTEL, CS, DS_RD, R/W_WR, IRQ and DTA_RDY).
The device supports the mandatory requirements of the IEEE-1149.1 (JTAG) standard via the test port.
4.0
The ZL50021 has 32 serial data inputs and 32 serial data outputs. Each stream can be individually programmed to
operate at 2.048, 4.096, 8.192 or 16.384 Mbps. Depending on the data rate there will be 32 channels, 64 channels,
128 channels or 256 channels, respectively, during a 125 µs frame.
The output streams can be programmed to operate as bi-directional streams. The output streams are divided into
two groups to be programmed into bi-directional mode. By setting BDL (bit 6) in the Internal Mode Selection (IMS)
register, input streams 0 - 15 (STi0 - 15) are internally tied low, and output streams 0 - 15 (STio0 - 15) are set to
operate in a bi-directional mode. Similarly, when BDH (bit 7) in the Internal Mode Selection (IMS) register is set,
input streams 16 - 31 (STi16 - 31) are internally tied low, and output streams 16 - 31 (STio16 - 31) are set to operate
in bi-directional mode. The groups do not have to be set into the same mode. Therefore it is possible to have half of
the streams operating in bi-directional mode while the other half is operating in normal input/output mode.
The input data rate is set on a per-stream basis by programming STIN[n]DR3 - 0 (bits 3 - 0) in the Stream Input
Control Register 0 - 31 (SICR0 - 31). The output data rate is set on a per-stream basis by programming STO[n]DR3
- 0 (bits 3 - 0) in the Stream Output Control Register 0 - 31 (SOCR0 - 31). The output data rates do not have to
match or follow the input data rates. The maximum number of channels switched is limited to 4096 channels. If all
32 input streams were operating at 16.384 Mbps (256 channels per stream), this would result in 8192 channels.
Memory limitations prevent the device from operating at this capacity. A maximum capacity of 4096 channels will
occur if half of the total streams are operating at 16.384 Mbps or all streams are operating at 8.192 Mbps. With all
streams operating at 4.096 Mbps, the switching capacity is reduced to 2048 channels. And with all streams
operating at 2.048 Mbps, the capacity will be further reduced to 1024 channels. However, as each stream can be
programmed to a different data rate, any combination of data rates can be achieved, as long as the total channel
count does not exceed 4096 channels. It should be noted that only full stream can be programmed for use. The
device does not allow fractional streams.
4.1
There are 16 external high impedance control signals, STOHZ0 - 15, that are used to control the external drivers for
per-channel high impedance operations. Only the first sixteen ST-BUS/GCI-Bus (STio0 - 15) outputs are provided
with corresponding STOHZ signals. The STOHZ outputs deliver the appropriate number of control timeslot
channels based on the output stream data rate. Each control timeslot lasts for one channel time. When the ODE pin
is high and the OSB (bit 2) of the Control Register (CR) is also high, STOHZ0 - 15 are enabled. When the ODE pin,
OSB (bit 2) of the Control Register (CR) or the RESET pin is low, STOHZ0 - 15 are driven high, together with all the
ST-BUS/GCI-Bus outputs being tristated. Under normal operation, the corresponding STOHZ outputs of any
unused ST-BUS/GCI-Bus channel (high impedance) are driven high. Refer to Figure 18 on page 34.
4.2
The input clock for the ZL50021 can be arranged in one of three different ways. These different ways will be
explained further in Section 11.1 to Section 11.3 on page 39. Depending on the mode of operation, the input clock,
CKi, will be based on the highest data rate of either the input or both the input and output data rates. The user has
External High Impedance Control, STOHZ0 - 15
Input Clock (CKi) and Input Frame Pulse (FPi) Timing
Data Rates and Timing
Zarlink Semiconductor Inc.
ZL50021
21
Data Sheet