ZL50022GAC ZARLINK [Zarlink Semiconductor Inc], ZL50022GAC Datasheet

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ZL50022GAC

Manufacturer Part Number
ZL50022GAC
Description
Enhanced 4 K Digital Switch with Stratum 4E DPLL
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
REF_FAIL0
REF_FAIL1
REF_FAIL2
REF_FAIL3
MODE_4M1
Features
MODE_4M0
STi[31:0]
OSC_EN
4096 channel x 4096 channel non-blocking digital
Time Division Multiplex (TDM) switch at
8.192 Mbps and 16.384 Mbps or using a
combination of ports running at 2.048, 4.096,
8.192 and 16.384 Mbps
32 serial TDM input, 32 serial TDM output
streams
Integrated Digital Phase-Locked Loop (DPLL)
exceeds Telcordia GR-1244-CORE Stratum 4E
specifications
Output clocks have less than 1 ns of jitter (except
for the 1.544 MHz output)
DPLL provides holdover, freerun and jitter
attenuation features with four independent
reference source inputs
REF0
REF1
REF2
REF3
CKi
FPi
V
DD_CORE
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,
S/P Converter
Input Timing
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08
OSC
DPLL
Copyright 2004-2005, Zarlink Semiconductor Inc. All Rights Reserved.
V
DD_IO
Figure 1 - ZL50022 Functional Block Diagram
V
DD_COREA
Microprocessor Interface
Zarlink Semiconductor Inc.
Internal Registers &
Connection Memory
V
Data Memory
DD_IOA
1
V
SS
Exceptional input clock cycle to cycle variation
tolerance (20 ns for all rates)
Output streams can be configured as bi-
directional for connection to backplanes
Per-stream input and output data rate conversion
selection at 2.048 Mbps, 4.096 Mbps, 8.192 Mbps
or 16.384 Mbps. Input and output data rates can
differ
Enhanced 4 K Digital Switch with
ZL50022GAC
ZL50022QCC
RESET
Ordering Information
P/S Converter
Output Timing
Test Port
Output HiZ
-40°C to +85°C
Control
ODE
256 Ball PBGA
256 Lead LQFP
Stratum 4E DPLL
Data Sheet
STio[31:0]
STOHZ[15:0]
FPo[3:0]
CKo[5:0]
FPo_OFF[2:0]
ZL50022
Trays
Trays
July 2005

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