ZL50022GAC ZARLINK [Zarlink Semiconductor Inc], ZL50022GAC Datasheet - Page 32

• Manufacturer Part Number: ZL50022GAC
• Description: Enhanced 4 K Digital Switch with Stratum 4E DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

7.3
This feature is used to advance the output data of individual output streams with respect to the output frame
boundary. Each output stream has its own bit advancement value which can be programmed in the Stream Output
Control Register 0 - 31 (SOCR0 - 31).
By default, all output streams have zero bit advancement such that bit 7 is the first bit that appears after the output
frame boundary (assuming ST-BUS formatting). The output advancement is enabled by STO[n]AD 2 - 0 (bits 6 - 4)
of the Stream Output Control Register 0 - 31 (SOCR0 - 31) as described in Table 47 on page 83. The output bit
advancement can vary from 0 to 7 bits.
FPi
STio[n]
Bit Adv = 0
(Default)
STio[n]
Bit Adv = 1
Output Advancement Programming
Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 Mbps modes respectively.
4 3
Last Channel
3
Last Channel
Figure 16 - Output Bit Advancement Timing Diagram (ST-BUS)
2 1 0
2 1 0
7
7
6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3
6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2
Bit Advancement = 1
Channel 0
Channel 0
Zarlink Semiconductor Inc.
ZL50022
32
Channel 1
Channel 1
Channel 2
Channel 2
Data Sheet
2 1