ZL50022GAC ZARLINK [Zarlink Semiconductor Inc], ZL50022GAC Datasheet - Page 39

• Manufacturer Part Number: ZL50022GAC
• Description: Enhanced 4 K Digital Switch with Stratum 4E DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

11.2
When the device is in Divided Slave mode, STio0 - 31 are driven by CKi. In this mode, the output streams and
clocks have the same jitter characteristics as the input clock (CKi), but the input and output data rates cannot
exceed the limit defined by CKi (as per Table 1). For example, if CKi is 4.096 MHz, the input and output data rate
cannot be higher than 2.048 Mbps, and the generated output clock rates cannot exceed 4.096 MHz. If the DPLL is
not enabled, an external oscillator is optional in Divided Slave mode.
11.3
When the device is in Multiplied Slave mode, device hardware is used to multiply CKi internally. STio0 - 31 are
driven by this internally generated clock. In this mode, the output clocks and data can run at any of the specified
rates, but they may have different jitter characteristics from the input clock (CKi). The input data rates are still
limited by the CKi rate (as per Table 1), as input data are always sampled directly by CKi. If the DPLL is not
enabled, an external oscillator is not required in Multiplied Slave mode.
12.0
The DPLL accepts four input references and delivers six output clocks and five output frame pulses. The DPLL
meets or exceeds all of the requirements of the Telcordia GR-1244-CORE standard for a Stratum 4E compliant
PLL. This includes the freerun, reference switching and monitoring, jitter/wander attenuation and holdover
functions. The intrinsic output jitter of the DPLL does not exceed 1 ns (except for the 1.544 MHz output).
The DPLL is able to lock to an input reference presented on the REF0 - 3 inputs. It is possible to force the DPLL
module to lock to a selected reference, to prefer one reference, to enter holdover mode or to freerun.
12.1
There are four timing modes for the DPLL: normal, holdover, automatic and freerun modes. In addition to these four
functional timing modes, the DPLL can also be programmed to internal reset mode.
12.1.1
In normal timing mode, the DPLL generates clocks and frame pulses that are phase locked to the active input
reference. Jitter on the input clock is attenuated by the DPLL.
12.1.2
In holdover mode, the DPLL no longer synchronizes the output clock to any input reference. It maintains the
frequency that it was at prior to entering holdover mode. The holdover mode typically happens when the input clock
becomes unreliable or is lost altogether. It takes some time for the system to realize that the input clock is
unreliable. Meanwhile, the DPLL tracks an unreliable clock. Therefore the DPLL could hold to an invalid frequency
when it enters holdover mode. In order to prevent this situation, the DPLL stores the current frequency at regular
intervals in holdover memory so that it can restore the frequency of the input clock just after the input clock became
unreliable.
12.1.3
In this mode, the state machine controls the DPLL based on the settings in the registers and the quality of the
reference input clocks. The DPLL is internally either in normal or holdover mode. In the following two sections, the
reference selection and state machine operation in automatic mode will be explained in more details.
Divided Slave Mode Operation
Multiplied Slave Mode Operation
DPLL Timing Modes
Overall Operation of the DPLL
Normal Mode
Holdover Mode
Automatic Mode
Zarlink Semiconductor Inc.
ZL50022
39
Data Sheet