ZL50023GAC ZARLINK [Zarlink Semiconductor Inc], ZL50023GAC Datasheet - Page 30

• Manufacturer Part Number: ZL50023GAC
• Description: Enhanced 4 K Digital Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

12.1
When the device is in Divided Clock mode, STio0 - 31 are driven by CKi. In this mode, the output streams and
clocks have the same amount of jitter as the input clock (CKi), but the output data rate cannot exceed the input data
rate defined by CKi. For example, if CKi is 4.096 MHz, the output data rate cannot be higher than 2.048 Mbps, and
the generated output clock rates cannot exceed 4.096 MHz.
12.2
When the device is in Multiplied Clock mode, device hardware is used to multiply CKi internally. STio0 - are driven
by this internally generated clock. In this mode, the output data rate can be any specified data rate, but the output
streams and clocks may have different jitter characteristics from the input clock (CKi).
13.0
The device provides access to the internal registers, connection memories and data memories via the
microprocessor port. The microprocessor port is capable of supporting both Motorola and Intel non-multiplexed
microprocessors. The microprocessor port consists of a 16-bit parallel data bus (D15 - 0), 14-bit address bus (A13 -
0) and six control signals (MOT_INTEL, CS, DS_RD, R/W_WR and DTA_RDY).
The data memory can only be read from the microprocessor port. For a data memory read operation, D7 - 0 will be
used and D15 - 8 will output zeros.
For a CM_L read or write operation, all bits (D15 - 0) of the data bus will be used. For a CM_H write operation, D4 -
0 of the data bus must be configured and D15 - 5 are ignored. D15 - 5 must be driven either high or low. For a
CM_H read operation, D4 - 0 will be used and D15 - 5 will output zeros.
Legend:
X
Reference Lock
Cki = Bypass. Cki is passed directly through to CKo0-3.
Cki MULT = Cki is passed through clock multiplier to CKo0-3.
Clock Source
Multiplied
Divided
Major
Clock
Clock
Operating Mode
Don’t care or not applicable.
Divided Clock Mode Performance
Multiplied Clock Mode Performance
Device
Microprocessor Port
Refers to what signal the output pins are locked to:
Refers to which clock samples STi and which clock outputs STo; STi applies when STio is input; STo applies when STio is output.
8/16 M
8/16 M
Minor
4 M
4 M
CKo0
CKo1
CKo2
CKo3
FPo0
FPo1
FPo2
FPo3
MODE_4M [1:0]
Control
11
00
11
00
Input Pins
4.096 MHz
8.192 MHz
16.384 MHz
4.096 MHz, 8.192 MHz, 16.384 MHz or 32.768 MHz
8 kHz (244 ns wide pulse)
8 kHz (122 ns wide pulse)
8 kHz (61 ns wide pulse)
8 kHz (244 ns, 122 ns, 61 ns or 30 ns wide pulse)
Table 9 - Generated Output Frequencies
Table 8 - ZL50023 Operating Modes
8/16 M
8/16 M
Signal
CKi
4 M
4 M
Zarlink Semiconductor Inc.
CR Register
ZL50023
OPM
Bit
0
1
30
Reference Lock
CKi MULT
CKo0-3
CKi
Output Clock Pins
Enabled
CKo0-3
Yes
CKi
STi
Clock Source
Data Sheet
Data Pins
(CKi MULT)
CKo0-3
CKo0-3
(CKi)
STo