ZL50023GAC ZARLINK [Zarlink Semiconductor Inc], ZL50023GAC Datasheet - Page 56
ZL50023GAC
Manufacturer Part Number
ZL50023GAC
Description
Enhanced 4 K Digital Switch
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.ZL50023GAC.pdf
(80 pages)
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Note 1:
Note 2:
15 - 5
3 - 2
1 - 0
Bit
15
4
0
For proper
Refer to G.711 standard for detail information of different laws.
14
0
OCL1 - 0
ICL1 - 0
Unused
Name
V/D
13
0
Table 35 - Connection Memory High (CM_H) Bit Assignment
µ-
law/A-law conversion, the CM_H bits should be set before Bit 15 of CM_L is set to high.
12
0
Reserved
In normal functional mode, these bits MUST be set to zero.
Voice/Data Control
When this bit is low, the corresponding channel is for voice.
When this bit is high, the corresponding channel is for data.
Input Coding Law.
Output Coding Law
11
0
ICL1-0
OCL1-0
00
01
10
11
10
0
00
01
10
11
Zarlink Semiconductor Inc.
9
0
For Voice (V/D bit = 0)
µ-law w/o Magnitude
For Voice (V/D bit = 0)
ZL50023
µ-law w/o Magnitude
CCITT.ITU A-law
CCITT.ITU µ-law
CCITT.ITU A-law
CCITT.ITU µ-law
A-law w/o ABI
8
0
A-law w/o ABI
Inversion
56
Inversion
7
0
Description
Output Coding Law
Input Coding Law
6
0
5
0
For Data (V/D bit = 1)
For Data (V/D bit = 1)
V/D
4
All Bits Inverted
All Bits Inverted
Inverted ABI
Inverted ABI
No code
No code
ICL
ABI
ABI
3
1
ICL
2
0
OCL
1
1
Data Sheet
OCL
0
0
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