ZL50031QEG1 ZARLINK [Zarlink Semiconductor Inc], ZL50031QEG1 Datasheet
ZL50031QEG1
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ZL50031QEG1 Summary of contents
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... Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2005, Zarlink Semiconductor Inc. All Rights Reserved. Flexible Channel Digital Switch with H.110 Interface and Local Switch Ordering Information ZL50031QEG1 *Pb Free Matte Tin -40°C to +85°C • Connection memory block-programming for fast device initialization • ...
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The device has features that are programmable on a per-stream or a per-channel basis including message mode, input delay offset, output advancement offset, and direction control. The ZL50031 supports all three of the H.110 specification required clocking modes: Primary Master, ...
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Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Holdover Frequency Stability ...
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Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 1 - Mode Selection for Backplane Streams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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HQFP Pinout Diagram 190 188 186 184 182 180 178 NC NC 194 NC NC 196 VDD5V VDD 198 BSTio15 BSTio14 200 BSTio13 BSTio12 202 VSS VDD 204 NC NC 206 BSTio11 BSTio10 208 BSTio9 BSTio8 210 VSS VDD 212 ...
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Pin Description 256 Pin HQFP Name 8,18,37, 62,70,78,89,95 101,107,113,120 135,145,156,164 172,180,198,204 212,220,231,243 253 155,187,197,229 V DD5V 7,17,36,43, 59,69,77,88,94 100,106,112,119 125,134,144 163,171,179,188 203,211,219,230 242,252 44 APLLV DD 45 APLLV SS 19 RESET 226 to 223 BSTio0-3, 218 ...
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Pin Description (continued) 256 Pin HQFP Name 143 TO 140 LSTi8 - 11 139 to 136 LSTi12 - 15 117 to 114 LSTo0 - 3 111 to 108 LSTo4 - 7 105 to 102 LSTo8 - ...
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Pin Description (continued) 256 Pin HQFP Name LREF0 - 3 66 NREFo 65 PRI_LOS 64 SEC_LOS 63 C32/64o 58 C1M5o 60 ST_FPo0 61 ST_CKo0 30 ST_FPo1 31 ST_CKo1 254 CS 255 DS 256 R ...
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Pin Description (continued) 256 Pin HQFP Name 154 PCI_OE 25,38,39,40,47, IC_GND 50,51,52,53,121, 122,123,124, 126,127,128,129, 130,131,132,133 26,27,28,29, IC_OPEN 32,33,34,35, 41,42 87 93, 118,157,158,165, 166,173,174, 181,182, 189 to196 205,206,213,214, 221,222,227, 228,232 24 TDi 20 TDo 22 TCK ...
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Device Overview The ZL50031 can switch up to 4,096 × 2,048 channels while providing a rate conversion capability designed to switch 64 kbps PCM kbps data between the backplane and local switching applications. ...
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FRAME_A_io, FRAME_B_io (CT Frame) C8_A_io, C8_B_io 8.192 MHz Ch 255 BSTio (16 Mbps mode) Figure 3 - ST-BUS Timing for 16 Mbps Backplane Data Streams 4.0 Switching Configuration The device has ...
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DMS Register Bits LG01 LG00 Table 2 - Mode Selection for Local LSTi0 - 3 and LSTo0 - 3 Streams, Group 0 DMS Register Bits LG11 LG10 ...
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DMS Register Bits LG31 Table 5 - Mode Selection for Local LSTi12 - 15 and LSTo12 - 15 Streams, Group 3 5.0 Local Input Delay Selection The local input delay selection allows individual local input streams ...
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Memory Block Programming The ZL50031 block programming mode (BPM) register provides users with the capability of initializing the local and backplane connection memories in two frames. Bit 13 - bit 15 of every backplane connection memory location will be ...
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For the local interface, the variable delay mode can be programmed through the local connection memory low bits, LTM2 - LTM0. When LTM2 - LTM0 are programmed to “000” per-channel variable delay from local input to local ...
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A13 - A0 0008 H 0009 H 000A H to 001B H 001C H 001D H 001E H 001F H 0020 H 0021 H 0022 H to 0026 H 0027 H 0028 H 0029 H 002A H 002B H 002C ...
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CT-Bus and local ST-BUS I/O drivers are controlled on a per-channel basis by backplane and local connection memories, respectively. By programming BTM2-0 bits to “110” in the backplane connection memory, the user can control the ...
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Local Connection Memory The local connection memory controls the local interface switching configuration. Locations in the local connection memory are associated with particular LSTo streams. The LTM2 - 0 bits of each local connection memory entry allow the per-channel ...
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LREF0-3 PRIMARY MASTER Network Ref (8 kHz / T1 / E1) Figure 5 - Typical Timing Control Configuration 15.1.1 Primary Master Mode In the Primary Master Mode, the ZL50031 drives the “A Clocks” (C8_A_io and FRAME_A_io), by locking to the ...
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Secondary Master Mode In the Secondary Master Mode, the ZL50031 drives the “B Clocks” (C8_B_io and FRAME_B_io), by locking to the “A Clocks”. As required by the H.110 standard, the “B Clocks” are edge-synchronous with the “A Clocks”, as ...
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DPLL Functional Description REF_SEL (RPS bit in DOM1) PRI_LOS Pin AUTODETECT (Selected by FDM0-1 bits in DOM2) SEC_LOS Pin FREQ_MOD_PRI Frequency (FP1-0 bits in DOM1) Mode FREQ_MOD_SEC MUX (FS1-0 bits in DOM1) PRI_REF Reference (Selected by SP3-0 bits Select ...
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PRI and SEC MUX Circuits The DPLL has four different modes to handle reference failure. These modes are selected by the FDM0 and FDM1 bits of the DOM2 Register. If FDM1-0 is ’10’ then the Primary reference is always ...
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State Machine Circuit The State Machine handles the reference selection. Depending on REF_SEL and LOS signals (selection between primary reference failure and PRI_LOS and between secondary reference failure and SEC_LOS), the state machine selects PRI_REF or SEC_REF as the ...
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Holdover Mode Holdover Mode is typically used for short durations while network synchronization is temporarily disrupted. If the FDM1-0 bits are programmed to ‘01’ in the DOM2 register and the PRI_LOS and SEC_LOS pins are high, the DPLL is ...
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Phase Locked Loop (PLL) Circuit As shown in Figure 8, "Block Diagram of the PLL Module" on page 27, the PLL module consists of a Skew Control, Maximum Time Interval Error (MTIE), Phase Detector, Phase Offset Adder, Phase Slope ...
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During a reference switch, the State Machine module first changes the mode of the DPLL from the Normal to the Holdover Mode. In the Holdover Mode, the DPLL no longer uses the virtual reference signal, but generates very accurate outputs ...
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Loop Filter The Loop Filter circuit gives frequency offset to the DCO circuit, based on the phase difference between the input and the feedback reference similar to a first order low pass filter, with two positions for ...
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When the reference frequency is either 2.048 MHz or 1.544 MHz, the CT_FRAME randomly defines the output frame boundary, always keeping the described relation to the CT_C8 clock. • When the reference frequency is 8.192 MHz, the output frame ...
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All outputs are derived from the same signal, therefore these diagrams apply to all outputs. Since 1 U.I. at 1.544 MHz (648 not equal to 1 U.I. at 2.048 MHz (488 ns PP output frequencies must be ...
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Figure 11 - Detailed DPLL Jitter Transfer Function Diagram 18.4 Frequency Accuracy Frequency accuracy is defined as the absolute tolerance of an output clock signal when the DPLL is not locked to an external reference, but is operating in the ...
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Phase Slope The phase slope or the phase alignment speed is the rate at which a given signal changes phase with respect to an ideal signal. The given signal is typically the output signal. The ideal signal is of ...
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JTAG Support The ZL50031 JTAG interface conforms to the Boundary-Scan IEEE1149.1 standard. The operation of the boundary-scan circuitry is controlled by an external Test Access Port (TAP) Controller. 20.1 Test Access Port (TAP) The Test Access Port (TAP) accesses ...
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Register Descriptions Read/Write Address: 0000 H Reset Value: 0000 STS3 STS2 STS1 STS0 Bit Name 15-14 Unused Reserved. 13-12 STS3-2 ST-BUS Frame Pulse and Clock Output Selection 1: These two bits ...
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Bit Name 2-0 MS2-0 Memory Select Bits: These three bits are used to select different connection and data memories. MS2 Table 8 - Control Register (CR) Bits (continued) Read/Write Address: 0001 H Reset Value: 0000 ...
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Bit Name 7-6 LG21-20 Local Group 2 Mode Select: These two bits refer to different switching modes for group 2 (LSTi8-11 and LSTo8-11) of the local interface. LG21 5 Unused Reserved. In normal functional mode, this bit MUST be set ...
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Bit Name 8-6 BBPD2-0 Backplane Block Programming Data Bits: These bits carry the value to be loaded into the backplane connection memory block whenever the Memory Block Programming feature is activated. After the MBP bit in the Control Register is ...
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Name LIDn4-0 Local Input Delay Bits These five bits define how long the serial interface receiver (See Note 1) takes to recognize and to store bit 0 from the LSTi The input delay can be selected to ...
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ST_FPo0/1 input data input data input data input data input data input data Note: The data is sampled at the 3/4 bit point. ZL50031 bit7 bit7 bit7 bit7 bit7 bit7 Figure 12 - Local Input Bit Delay Timing 40 Zarlink ...
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Read/Write Addresses: 001C H 001E H Reset value: 0000 BOAR0 BOA BOA BOA BOA BOAR1 BOA BOA BOA BOA 151 150 141 140 BOAR2 BOA BOA BOA BOA 231 230 221 ...
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Read/Write Addresses: Reset value LOAR0 LOA LOA LOA LOA LOA LOAR1 LOA1 LOA1 LOA1 LOA1 LOA1 Name LOAn1-0 Local Output Advancement Bits 1-0: These two ...
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Read/Write Address: 0027 H Reset Value: 0000 LBS LBS A3 A2 Bit Name Unused Reserved. In normal functional mode, these bits MUST be set to zero. ...
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Read Address: 002A H Reset Value: 0000 BBER BBER BBER BBER BBER Bit Name BBER15 -0 Backplane Bit Error Rate Count Bits: These bits refer to ...
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Read/Write Address: 002B H Reset Value: 0000 CNEN BEN AEN RPS FS1 Bit Name FP1 - 0 PRI_REF Frequency Selection Bits: These bits are used to select different clock frequencies for ...
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Read/Write Address: 002B H Reset Value: 0000 CNEN BEN AEN RPS FS1 Bit Name SP3 - 0 Primary Clock Reference Input Selection Bits: These bits are used to select primary reference ...
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Read/Write Address: 002C r H Reset Value: 0000 HRST MRST Bit Name Unused Reserved. In normal functional mode, these bits MUST be set to zero. 11 ...
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Bit Name 4 -3 DIV1 - 0 Divider Bits: These two bits define the relationship between the input reference and the NREFo output. DIV1 Reserved Reserved. In normal functional mode, this bit MUST be set ...
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Primary Master Bit BEN (bit 14 Monitor “B Clocks” AEN (bit 13 Drive “A Clocks” RPS (bit 12 Preferred reference is PRI_REF FS1 kHz (bits 11-10 1.544 MHz Frequency ...
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Read/Write Address: 002D H Reset Value: 0000 POS POS POS POS POS Bit Name POS6 - 0 Phase Offset Bits: These seven bits refer to the ...
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BTM BTM BTM BSAB BSAB Bit Name 15 -13 BTM2 - 0 Throughput Delay and Message Control Bits: These three bits control the backplane CT-Bus input or output. BTM 2-0 ...
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Bit Name BCAB7 - 0 Source Channel Address Bits: These eight bits refer to the number of the channel for (See the source (backplane or local) connection. Note 1) Note 1: Only Bits 7-0 will be used ...
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LTM LTM LTM LSAB LSAB Bit Name 15 -13 LTM2 - 0 Throughput Delay and Message Channel Control Bits: These three bits control the local ST-BUS output. LTM2-0 000 001 ...
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Data Rate Source Stream 8 Mbps BSTio0-31 16 Mbps BSTio0-15 Table 28 - LSAB and LCAB Bits Usage when Source Stream is from the Backplane Port Data Rate Source Stream 2 Mbps LSTi0-15 4 Mbps LSTi0-15 8 Mbps LSTi0-15 Table ...
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DC/AC Electrical Characteristics Absolute Maximum Ratings* Parameter 1 Supply Voltage 2 BSTio Bias Voltage 3 Input Voltage 4 Output Voltage 5 Package power dissipation 6 Storage temperature * Exceeding these values may cause permanent damage. Functional operation under these ...
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AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels Characteristics 1 CMOS Threshold 2 Rise/Fall Threshold Voltage High 3 Rise/Fall Threshold Voltage Low † AC Electrical Characteristics - Input Frame Pulse and Input Clock Timing Characteristic 1 FRAME_A_io, FRAME_B_io Input ...
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AC Electrical Characteristics - Output Frame Pulse and Output Clock Timing Characteristic 1 Backplane Frame Boundary Offset 2 FRAME_A_io, FRAME_B_io Output Pulse Width 3 Delay from FRAME_A_io, FRAME_B_io output falling edge to C8_a_io,C8_B_io output rising edge 4 Delay from ...
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Backplane Frame Boundary FRAME_A_io, FRAME_B_io (OUTPUT) t C8MH C8_A_io, C8_B_io (OUTPUT) t C32ML C32/64o (32.768 MHz C64ML C64MH C32/64o (65.536 MHz) Figure 16 - Backplane Frame Pulse Output and Clock Output Timing Diagram (in Primary Master † AC ...
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AC Electrical Characteristics - Reference Input Timing Characteristic 1 CTREF1, CTREF2, LREF0-3 Period 2 CTREF1, CTREF2, LREF0-3 High Time 3 CTREF1, CTREF2, LREF0-3 Low Time 4 CTREF1, CTREF2, LREF0-3 Rise/Fall Time 5 CTREF1, CTREF2, LREF0-3 Period 6 CTREF1, CTREF2, ...
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AC Electrical Characteristics - Reference Output Timing Characteristic 1 NREFo Output Delay Time 2 NREFo Clock Period 3 NREFo Clock High Time 4 NREFo Clock Low Time 5 NREFo Clock Rise/Fall Time 6 NREFo Clock Period 7 NREFo Clock ...
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LREF0-3 t ROD (1.544 MHz) t R8KO15L NREFo (8 kHz) t rREF Figure 25 - Reference Output Timing Diagram when (DIV1, DIV0 DOM2 Register † AC Electrical Characteristics - Local Frame Pulse and Clock Timing, Characteristic ...
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AC Electrical Characteristics - Local Frame Pulse and Clock Timing, Characteristic 1 Local Frame Boundary Offset 2 ST_FPo0/1 Width 3 ST_FPo0/1 Output Delay from Falling edge of ST_FPo0/1 to falling edge of ST_CKo0/1 4 ST_FPo0/1 Output Delay from Falling ...
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AC Electrical Characteristics - Local Frame Pulse and Clock Timing, Characteristic 1 Local Frame Boundary Offset 2 ST_FPo0/1 Width 3 ST_FPo0/1 Output Setup from Falling edge of ST_FPo0/1 to falling edge of ST_CKo0/1 4 ST_FPo Output Hold from Falling ...
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AC Electrical Characteristics Characteristic 1 C1M5o Period 2 C1M5o High Time 3 C1M5o Low Time 4 C1M5o Rise Time 5 C1M5o Fall Time † Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25°C and ...
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AC Electrical Characteristics - Backplane Serial Streams with Date Rate of 8 Mbps Characteristic 1 BSTio0-31 Input Data Sample Point 2 BSTio0-31 Input Setup Time 3 BSTio0-31 Input Hold Time 4 BSTio0-31 Output Delay Active to Active 5 Per ...
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AC Electrical Characteristics - Backplane Serial Streams with Date Rate of 16 Mbps Characteristic 1 BSTio0-15 Input Data Sample Point 2 BSTio0-15 Input Setup Time 3 BSTio0-15 Input Hold Time 4 BSTio0-15 Output Delay Active to Active † Characteristics ...
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AC Electrical Characteristics Characteristic 1 LSTo Delay - Active to Active @2.048 Mbps @4.096 Mbps @8.192 Mbps † Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25°C and are for design aid only: ...
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AC Electrical Characteristics - Local Serial Stream Input Timing Characteristic 1 LSTi Input Data Sample Point @2.048 Mbps @4.096 Mbps @8.192 Mbps 2 LSTi Setup Time @2.048 Mbps @4.096 Mbps @8.192 Mbps 3 LSTi Hold Time @2.048 Mbps @4.096 ...
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AC Electrical Characteristics - Local and Backplane Tristate Timing Characteristic 1 LSTo/BSTio Delay - Active to High-Z - High-Z to Active 2.048 Mbps (local) 4.096 Mbps (local) 8.192 Mbps (local) 8.192 Mbps (backplane) 16.384 Mbps (backplane) 2 Output Driver ...
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LSTo/BSTio (Output) † AC Electrical Characteristics - Motorola Non-Multiplexed Bus Mode Characteristics 1 CS setup from DS falling 2 R/W setup from DS falling 3 Address setup from DS falling 4 CS hold after DS rising 5 R/W hold after ...
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DS CS R/W A0-A13 D0-D15 READ D0-D15 WRITE DTA Figure 37 - Motorola Non-Multiplexed Bus Timing † AC Electrical Characteristics - JTAG Test Port and Reset Pin Timing Characteristic 1 TCK Clock Period 2 TCK Clock Pulse Width High 3 ...
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TCK t TMSS TMS t TDIS TDi TDo TRST Reset 23.0 Trademarks ® CompactPCI is a registered trademark of PICMG-PCI Industrial Computer Manufacturers Group, Inc. ZL50031 t t TCKL TCKH t TCKP t TMSH t TDIH Figure 38 - JTAG ...
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