ZL50031QEG1 ZARLINK [Zarlink Semiconductor Inc], ZL50031QEG1 Datasheet - Page 20

• Manufacturer Part Number: ZL50031QEG1
• Description: Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 2 K x 2 K Local Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

13.0
The local connection memory controls the local interface switching configuration. Locations in the local connection
memory are associated with particular LSTo streams.
The LTM2 - 0 bits of each local connection memory entry allow the per-channel selection from message mode,
connection mode, constant delay, variable delay or bit error test mode. See Table 27 on page 53 for the per-
channel control functions.
In the switching mode, the contents of the local connection memory stream address bits (LSAB4-0) and the channel
address bits (LCAB7-0) define the source information (stream and channel) of the time slot that will be switched to
the local LSTo streams. During message mode, only the 8 least significant bits of the local connection memory low
bits are transferred to the LSTo pins.
14.0
The ZL50031 offers users a Bit Error Rate (BER) test feature for the backplane and the local interfaces. The
circuitry of the BER test consists of a transmitter and a receiver on both interfaces that can transmit and receive the
BER patterns independently. The transmitter can output a pseudo-random pattern of the form 2
and any stream within a frame. For the test, users can program the output channel and stream through the
backplane or local connection memory and the input channel and stream using Local or Backplane BER Input
Selection (BIS) registers. See Table 15 on page 43 and Table 17 on page 43 for the LBIS and the BBIS registers
contents, respectively.
The receiver receives the BER pattern and does an internal BER pattern comparison. For backplane interface, the
comparison result is stored in the Backplane BER register (BBERR). For local interface, the result is stored in the
Local BER register (LBERR).
15.0
The Digital Phase Locked Loop (DPLL) accepts selectable 2.048 MHz, 1.544 MHz or 8 kHz input reference signals.
It accepts reference inputs from independent sources and provides bit-error-free reference switching. The DPLL
meets phase slope and MTIE requirements defined by the Telcordia GR-1244-CORE standard.
The DPLL also provides the timing for the rest of the ZL50031 Digital Switch, generating several network clocks
with the appropriate quality. Clocks are synchronized to one of two input reference clocks and meet the
requirements of the H.110 clock specification.
15.1
The DPLL, and consequently the ZL50031, can, as required by the H.110 standard, operate in three different
modes: Primary Master, Secondary Master and Slave. See Figure 5, "Typical Timing Control Configuration" on
page 21.
To configure the DPLL, there are two Operation Mode registers: DOM1 and DOM2. See Table 19 on page 44 and
Table 20 on page 47 for the contents of these registers.
In all modes the ZL50031 monitors both the “A Clocks” (C8_A_io and FRAME_A_io) and the “B Clocks” (C8_B_io
and FRAME_B_io). The Fail_A and the Fail_B signals indicate the quality of the “A Clocks” and “B Clocks”
respectively.
ZL50031 Modes of Operation
Local Connection Memory
Bit Error Rate Test
DPLL
Zarlink Semiconductor Inc.
ZL50031
20
15
- 1 to any channel
Data Sheet