ZL50052GAC ZARLINK [Zarlink Semiconductor Inc], ZL50052GAC Datasheet - Page 19

• Manufacturer Part Number: ZL50052GAC
• Description: 8 K Channel Digital Switch with High Jitter Tolerance, Single Rate (32 Mbps), and 16 Inputs and 16 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

When SMPL_MODE = LOW (input bit fractional delay mode) , bits LID[4:0] and BID[4:0] in the LIDR0 - 7 and
BIDR0 - 7 registers respectively define the input bit fractional delay of the corresponding Local and Backplane
stream. The total delay can be up to 7 3/4 bits with a resolution of 1/4 bit at the selected data rate. When
SMPL_MODE = HIGH (sampling point select mode), bits LID[1:0] and BID[1:0] define the input bit sampling point of
the stream. The sampling point can be programmed at the 3/4, 4/4, 1/4 or 2/4 bit location to allow better tolerance
for input jitter. Bits LID[4:2] and BID[4:2] define the integer input bit delay, with a maximum value of 7 bits at a
resolution of 1 bit.
Refer to Figure 8 for Input Bit Delay Timing at 32 Mbps data rates.
Refer to Figure 9 for Input Sampling Point Selection Timing at 32 Mbps data rates.
SMPL_MODE = LOW
Please refer to Control Register (Section 13.1) for SMPL_MODE definition.
Figure 8 - Backplane and Local Input Bit Delay Timing Diagram for Data Rate of 32 Mbps
Bit Delay = 7 1/2
Bit Delay = 7 3/4
Bit Delay = 1/4
Bit Delay = 1/2
Bit Delay = 3/4
BSTi/LSTi0-7
BSTi/LSTi0-7
BSTi/LSTi0-7
BSTi/LSTi0-7
BSTi/LSTi0-7
BSTi/LSTi0-7
BSTi/LSTi0-7
Bit Delay = 0
Bit Delay = 1
(Default)
FP8i
C8i
3
Ch510
3
Ch510
3
Ch511
2
3
2
Ch511
Ch511
2
3
Ch511
2
Ch511
2
1
2
1
1
2
1
1
0
1
0
0
1
0
Zarlink Semiconductor Inc.
0
7
0
7
0
7
ZL50052
7
Bit Delay, 1/4
7
6
Bit Delay, 1/2
7
6
Bit Delay, 3/4
6
7
Bit Delay, 1
6
19
6
5
6
5
5
6
5
Ch511
5
Ch511
4
Ch0
5
4
4
Ch0
5
Ch0
4
Ch0
3
4
Ch0
3
4
3
4
3
3
2
3
2
2
3
2
2
1
2
1
1
2
1
1
0
1
0
0
1
0
0
7
0
Bit Delay, 7 1/2
7
7
0
Bit Delay, 7 3/4
7
7
6
7
6
6
7
6
6
Ch0
5
6
Ch0
5
Ch1
5
6
Ch1
Ch1
5
Ch1
5
4
Ch1
5
4
4
5
Data Sheet
4
4
4