ZL50052GAC ZARLINK [Zarlink Semiconductor Inc], ZL50052GAC Datasheet - Page 27

• Manufacturer Part Number: ZL50052GAC
• Description: 8 K Channel Digital Switch with High Jitter Tolerance, Single Rate (32 Mbps), and 16 Inputs and 16 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

10.1
The Test Access Port (TAP) consists of four input pins and one output pin described as follows:
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10.2
The ZL50052 implements the public instructions defined in the IEEE-1149.1 standard with the provision of an
Instruction Register and three Test Data Registers.
10.2.1
The JTAG interface contains a 4-bit instruction register. Instructions are serially loaded into the Instruction Register
from the TDi pin when the TAP Controller is in the shift-IR state. Instructions are subsequently decoded to achieve
two basic functions: to select the Test Data Register to operate while the instruction is current, and to define the
serial Test Data Register path to shift data between TDi and TDo during data register scanning. Please refer to
Figure 24 for JTAG test port timing.
10.2.2
10.2.2.1
The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path around the
boundary of the ZL50052 core logic.
10.2.2.2
The Bypass register is a single stage shift register to provide a 1-bit path from TDi to TDo.
Test Clock Input (TCK)
TCK provides the clock for the TAP Controller and is independent of any on-chip clock. TCK permits the
shifting of test data into or out of the Boundary-Scan register cells under the control of the TAP Controller in
Boundary-Scan Mode.
Test Mode Select Input (TMS)
The TAP controller uses the logic signals applied to the TMS input to control test operations. The TMS
signals are sampled at the rising edge of the TCK pulse. This pin in internally pulled to V
driven from an external source.
Test Data Input (TDi)
Depending on the previously applied data to the TMS input, the serial input data applied to the TDi port is
connected either to the Instruction Register or to a Test Data Register. Both registers are described in
Section 10.2, TAP Registers. The applied input data is sampled at the rising edge of TCK pulses. This pin is
internally pulled to V
Test Data Output (TDo)
Depending on the previously applied sequence to the TMS input, the contents of either the instruction
register or data register are serially shifted out towards the TDo. The data out of the TDo is clocked on the
falling edge of the TCK pulses. When no data is shifted through the boundary scan cells, the TDo output is
set to a high impedance state.
Test Reset (TRST)
TRST provides an asynchronous Reset to the JTAG scan structure. This pin is internally pulled high when
not driven from an external source. This pin MUST be pulled low for normal operation.
Test Access Port (TAP)
TAP Registers
Test Instruction Register
Test Data Registers
The Boundary-Scan Register
The Bypass Register
DD_IO
when not driven from an external source.
Zarlink Semiconductor Inc.
ZL50052
27
DD_IO
Data Sheet
when not